* [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
` (11 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven,
Damien Le Moal
"make dtbs_check":
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'
From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
Fix this by renaming all SPI FLASH nodes to "flash".
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
v2:
- Add Reviewed-by, Tested-by.
---
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
index 0bcaf35045e795ed..984872f3d3a9b9ea 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
@@ -199,7 +199,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
index ac8a03f5867adbd0..7ba99b4da304218e 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
@@ -201,7 +201,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
index 623998194bc18aab..be9b12c9b374acb3 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
@@ -209,7 +209,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
index cf605ba0d67e43cd..031c0c28f8195777 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
@@ -174,7 +174,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
` (10 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven,
Damien Le Moal
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
v2:
- Add Reviewed-by, Tested-by.
---
arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5e8ca8142482153b..56f57118c633b91a 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -103,8 +103,8 @@ rom0: nvmem@1000 {
clint0: timer@2000000 {
compatible = "canaan,k210-clint", "sifive,clint0";
reg = <0x2000000 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
plic0: interrupt-controller@c000000 {
@@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 {
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
riscv,ndev = <65>;
};
@@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 {
compatible = "canaan,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
- interrupts = <34 35 36 37 38 39 40 41
- 42 43 44 45 46 47 48 49
- 50 51 52 53 54 55 56 57
- 58 59 60 61 62 63 64 65>;
+ interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>, <45>, <46>, <47>,
+ <48>, <49>, <50>, <51>, <52>, <53>, <54>,
+ <55>, <56>, <57>, <58>, <59>, <60>, <61>,
+ <62>, <63>, <64>, <65>;
gpio-controller;
ngpios = <32>;
};
@@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 {
dmac0: dma-controller@50000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
- interrupts = <27 28 29 30 31 32>;
+ interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
clock-names = "core-clk", "cfgr-clk";
@@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 {
timer0: timer@502d0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
- interrupts = <14 15>;
+ interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
@@ -326,7 +327,7 @@ timer0: timer@502d0000 {
timer1: timer@502e0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
- interrupts = <16 17>;
+ interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
@@ -336,7 +337,7 @@ timer1: timer@502e0000 {
timer2: timer@502f0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
- interrupts = <18 19>;
+ interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
` (9 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
It does not make sense to have an (empty) chosen node in an SoC-specific
.dtsi, as chosen is meant for system-specific configuration.
It is already provided in microchip-mpfs-icicle-kit.dts anyway.
Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v2:
- Add Reviewed-by.
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c9f6d205d2ba1a5e..794da883acb19256 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -9,9 +9,6 @@ / {
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";
- chosen {
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (2 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
` (8 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
Fix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v2:
- Add Reviewed-by.
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 794da883acb19256..ee59751544a0d3bc 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -168,16 +168,17 @@ &cpu3_intc 3 &cpu3_intc 7
};
plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev = <186>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11
&cpu1_intc 11 &cpu1_intc 9
&cpu2_intc 11 &cpu2_intc 9
&cpu3_intc 11 &cpu3_intc 9
&cpu4_intc 11 &cpu4_intc 9>;
+ riscv,ndev = <186>;
};
dma@3000000 {
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (3 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 14:39 ` Conor.Dooley
2021-12-16 13:37 ` [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven
` (7 subsequent siblings)
12 siblings, 1 reply; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
"make dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous
"clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not
set until bitstream programming time.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
v2:
- Add Acked-by,
- Move clock-frequency to board DTS.
---
.../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++-------
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index fc1e5869df1b9fc5..0c748ae1b0068df7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -35,6 +35,10 @@ memory@80000000 {
};
};
+&refclk {
+ clock-frequency = <600000000>;
+};
+
&serial0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index ee59751544a0d3bc..b372bc6459bf163a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller {
};
};
+ refclk: msspllclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -189,13 +194,6 @@ dma@3000000 {
#dma-cells = <1>;
};
- refclk: refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- clock-output-names = "msspllclk";
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node
2021-12-16 13:37 ` [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
@ 2021-12-16 14:39 ` Conor.Dooley
0 siblings, 0 replies; 40+ messages in thread
From: Conor.Dooley @ 2021-12-16 14:39 UTC (permalink / raw)
To: geert, paul.walmsley, palmer, aou
Cc: robh+dt, damien.lemoal, Lewis.Hanly, krzysztof.kozlowski,
linux-riscv, devicetree
On 16/12/2021 13:37, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> "make dtbs_check" reports:
>
> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
> From schema: dtschema/schemas/simple-bus.yaml
>
> Fix this by moving the node out of the "soc" subnode.
> While at it, rename it to "msspllclk", and drop the now superfluous
> "clock-output-names" property.
> Move the actual clock-frequency value to the board DTS, since it is not
> set until bitstream programming time.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Looks good to me.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v2:
> - Add Acked-by,
> - Move clock-frequency to board DTS.
> ---
> .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++-------
> 2 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> index fc1e5869df1b9fc5..0c748ae1b0068df7 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> @@ -35,6 +35,10 @@ memory@80000000 {
> };
> };
>
> +&refclk {
> + clock-frequency = <600000000>;
> +};
> +
> &serial0 {
> status = "okay";
> };
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index ee59751544a0d3bc..b372bc6459bf163a 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller {
> };
> };
>
> + refclk: msspllclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> soc {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -189,13 +194,6 @@ dma@3000000 {
> #dma-cells = <1>;
> };
>
> - refclk: refclk {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <600000000>;
> - clock-output-names = "msspllclk";
> - };
> -
> clkcfg: clkcfg@20002000 {
> compatible = "microchip,mpfs-clkcfg";
> reg = <0x0 0x20002000 0x0 0x1000>;
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (4 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 14:47 ` Conor.Dooley
2021-12-16 13:37 ` [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Geert Uytterhoeven
` (6 subsequent siblings)
12 siblings, 1 reply; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
Fix the device node for the clock controller:
- Remove bogus "reg-names" property,
- Remove unneeded "clock-output-names" property.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
v2:
- New.
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b372bc6459bf163a..d9c1dee3fb25beb8 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -197,17 +197,8 @@ dma@3000000 {
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
- reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;
- clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
- "mac0", "mac1", "mmc", "timer", /* 4-7 */
- "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
- "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
- "i2c1", "can0", "can1", "usb", /* 16-19 */
- "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
- "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
- "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
};
serial0: serial@20000000 {
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node
2021-12-16 13:37 ` [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven
@ 2021-12-16 14:47 ` Conor.Dooley
0 siblings, 0 replies; 40+ messages in thread
From: Conor.Dooley @ 2021-12-16 14:47 UTC (permalink / raw)
To: geert, paul.walmsley, palmer, aou
Cc: robh+dt, damien.lemoal, Lewis.Hanly, krzysztof.kozlowski,
linux-riscv, devicetree
On 16/12/2021 13:37, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Fix the device node for the clock controller:
> - Remove bogus "reg-names" property,
> - Remove unneeded "clock-output-names" property.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Ha, doing my job for me again - was hoping to send my v2 tomorrow too so
good timing on your part.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
(I have booted the 5 patches for the polarfire on my board, so
Tested-by: Conor Dooley <conor.dooley@microchip.com> too?)
> ---
> v2:
> - New.
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index b372bc6459bf163a..d9c1dee3fb25beb8 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -197,17 +197,8 @@ dma@3000000 {
> clkcfg: clkcfg@20002000 {
> compatible = "microchip,mpfs-clkcfg";
> reg = <0x0 0x20002000 0x0 0x1000>;
> - reg-names = "mss_sysreg";
> clocks = <&refclk>;
> #clock-cells = <1>;
> - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
> - "mac0", "mac1", "mmc", "timer", /* 4-7 */
> - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
> - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
> - "i2c1", "can0", "can1", "usb", /* 16-19 */
> - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
> - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
> - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
> };
>
> serial0: serial@20000000 {
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (5 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 08/11] riscv: dts: sifive: " Geert Uytterhoeven
` (5 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v2:
- Add Reviewed-by.
---
.../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++---------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d9c1dee3fb25beb8..869aaf0d5c066c9d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -158,18 +158,18 @@ cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7
- &cpu2_intc 3 &cpu2_intc 7
- &cpu3_intc 3 &cpu3_intc 7
- &cpu4_intc 3 &cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
};
plic: interrupt-controller@c000000 {
@@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11
- &cpu1_intc 11 &cpu1_intc 9
- &cpu2_intc 11 &cpu2_intc 9
- &cpu3_intc 11 &cpu3_intc 9
- &cpu4_intc 11 &cpu4_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
riscv,ndev = <186>;
};
@@ -190,7 +190,8 @@ dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
#dma-cells = <1>;
};
@@ -254,7 +255,7 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88 89>;
+ interrupts = <88>, <89>;
clocks = <&clkcfg 6>;
max-frequency = <200000000>;
status = "disabled";
@@ -264,7 +265,7 @@ emac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
interrupt-parent = <&plic>;
- interrupts = <64 65 66 67>;
+ interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 4>, <&clkcfg 2>;
clock-names = "pclk", "hclk";
@@ -277,7 +278,7 @@ emac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
interrupt-parent = <&plic>;
- interrupts = <70 71 72 73>;
+ interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 5>, <&clkcfg 2>;
status = "disabled";
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 08/11] riscv: dts: sifive: Group tuples in interrupt properties
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (6 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
` (4 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
v2:
- Add Reviewed-by.
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++----------
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++-------
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 0655b5c4201d9f71..0caca0ccf6711ded 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <53>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
@@ -170,7 +170,8 @@ dma: dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic0>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
#dma-cells = <1>;
};
uart1: serial@10011000 {
@@ -243,7 +244,7 @@ pwm0: pwm@10020000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <42 43 44 45>;
+ interrupts = <42>, <43>, <44>, <45>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
@@ -252,7 +253,7 @@ pwm1: pwm@10021000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <46 47 48 49>;
+ interrupts = <46>, <47>, <48>, <49>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
@@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index abbb960f90a00ac2..8464b0e3c88791e1 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <69>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu740-c000-prci";
@@ -273,7 +273,7 @@ ccache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <19 21 22 20>;
+ interrupts = <19>, <21>, <22>, <20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (7 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 08/11] riscv: dts: sifive: " Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
` (3 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in "reg" properties containing register blocks should be grouped using
angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
v2:
- Add Reviewed-by.
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 0caca0ccf6711ded..e2efcf08210926f8 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -196,8 +196,8 @@ i2c0: i2c@10030000 {
};
qspi0: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000
- 0x0 0x20000000 0x0 0x10000000>;
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <51>;
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -207,8 +207,8 @@ qspi0: spi@10040000 {
};
qspi1: spi@10041000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000
- 0x0 0x30000000 0x0 0x10000000>;
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -230,8 +230,8 @@ eth0: ethernet@10090000 {
compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>;
interrupts = <53>;
- reg = <0x0 0x10090000 0x0 0x2000
- 0x0 0x100a0000 0x0 0x1000>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (8 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Geert Uytterhoeven
` (2 subsequent siblings)
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
"make dtbs_check":
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00']
'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00']
'sifive,fu540-c000' was expected
'sifive,fu740-c000' was expected
'sifive,fu540' was expected
'sifive,fu740' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
This happens because the "soc" subnode declares compatibility with
"sifive,fu540-c000" and "sifive,fu540", while these are only intended
for the root node.
Fix this by removing the bogus compatible values from the "soc" node.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
v2:
- Add Reviewed-by.
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index e2efcf08210926f8..b1250c16816f5c9d 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -137,7 +137,7 @@ cpu4_intc: interrupt-controller {
soc {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (9 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
12 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Geert Uytterhoeven
Fix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
v2:
- New.
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index b1250c16816f5c9d..3eef52b1a59b5cb4 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -140,10 +140,10 @@ soc {
compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev = <53>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
interrupt-controller;
interrupts-extended =
<&cpu0_intc 0xffffffff>,
@@ -151,6 +151,7 @@ plic0: interrupt-controller@c000000 {
<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
+ riscv,ndev = <53>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
--
2.25.1
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^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (10 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
` (4 more replies)
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
12 siblings, 5 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, David Airlie,
Daniel Vetter, Rob Herring
Cc: Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley,
linux-riscv, devicetree, Biju Das, dri-devel, Alyssa Rosenzweig,
Steven Price, tomeu.vizoso, Robin Murphy, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 +
out of tree patch for (du + DSI) +
platform specific mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Platform specific mesa configuration patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V2->V3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L
SoC-specific conditional schemas.
* Updated commit description for patch#3
V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
3 files changed, 121 insertions(+), 2 deletions(-)
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
@ 2021-12-16 13:41 ` Geert Uytterhoeven
2021-12-16 13:43 ` Geert Uytterhoeven
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:41 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Sagar Kadam, David Airlie, Daniel Vetter
Cc: linux-kernel, devicetree, linux-riscv, Biju Das, dri-devel,
Alyssa Rosenzweig, Steven Price, tomeu.vizoso, Robin Murphy,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 +
out of tree patch for (du + DSI) +
platform specific mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Platform specific mesa configuration patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V2->V3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L
SoC-specific conditional schemas.
* Updated commit description for patch#3
V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
3 files changed, 121 insertions(+), 2 deletions(-)
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
@ 2021-12-16 13:43 ` Geert Uytterhoeven
2021-12-16 13:46 ` Geert Uytterhoeven
` (2 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:43 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Anup Patel, David Airlie, Daniel Vetter
Cc: linux-kernel, devicetree, linux-riscv, Biju Das, dri-devel,
Alyssa Rosenzweig, Steven Price, tomeu.vizoso, Robin Murphy,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 +
out of tree patch for (du + DSI) +
platform specific mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Platform specific mesa configuration patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V2->V3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L
SoC-specific conditional schemas.
* Updated commit description for patch#3
V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
3 files changed, 121 insertions(+), 2 deletions(-)
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
2021-12-16 13:43 ` Geert Uytterhoeven
@ 2021-12-16 13:46 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:46 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, David Airlie,
Daniel Vetter, Rob Herring
Cc: Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley,
linux-riscv,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Biju Das, DRI Development, Alyssa Rosenzweig, Steven Price,
Tomeu Vizoso, Robin Murphy, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
On Thu, Dec 16, 2021 at 2:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> RZ/G2L SoC embeds Mali-G31 bifrost GPU.
> This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
` (2 preceding siblings ...)
2021-12-16 13:46 ` Geert Uytterhoeven
@ 2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:47 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Sagar Kadam, David Airlie, Daniel Vetter
Cc: Linux Kernel Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, Biju Das, DRI Development, Alyssa Rosenzweig,
Steven Price, Tomeu Vizoso, Robin Murphy, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
On Thu, Dec 16, 2021 at 2:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> RZ/G2L SoC embeds Mali-G31 bifrost GPU.
> This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
` (3 preceding siblings ...)
2021-12-16 13:47 ` Geert Uytterhoeven
@ 2021-12-16 13:47 ` Geert Uytterhoeven
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:47 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Anup Patel, David Airlie, Daniel Vetter
Cc: Linux Kernel Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, Biju Das, DRI Development, Alyssa Rosenzweig,
Steven Price, Tomeu Vizoso, Robin Murphy, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
On Thu, Dec 16, 2021 at 2:44 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> RZ/G2L SoC embeds Mali-G31 bifrost GPU.
> This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
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^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (11 preceding siblings ...)
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
@ 2021-12-16 13:37 ` Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
` (4 more replies)
12 siblings, 5 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:37 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Pratyush Yadav, Michael Walle,
linux-mtd
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv, devicetree, Miquel Raynal,
linux-renesas-soc, Magnus Damm, Gareth Williams, Phil Edworthy,
Geert Uytterhoeven, Thomas Petazzoni, Milan Stevanovic,
Jimmy Lalande
From: Miquel Raynal <miquel.raynal@bootlin.com>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND
controller.
This time the driver has been tested with a fully-upstream device tree
on top of a v5.16-rc4. The DT used is very close to the r9a06g032-db.
Cheers,
Miquèl
Changes in v4:
* Set unevaluatedProperties set to false in the bindings.
* Change the clock names by removing the nand_ prefix which is
redundant, even though the clocks are named like this in the spec. The
name remains clear enough anyway.
Changes in v3:
* Rebased on top of a fully-upstream recent kernel.
* Renamed the clocks in the bindings and the driver to match the
documentation (lower-cased): nand_hclk & nand_eclk.
* Added a new commit describing the NAND controller in the r9a06g032
DTSI.
* Added the Reviewed-by and Tested-by tags received.
Changes in v2:
* Added the family-specific rzn1 compatible as suggested by Geert.
Updated the bindings, the binding file name, the compatible used in
the driver, the MAINTAINERS entry, etc.
* Added an ARCH_RENESAS Kconfig dependency.
* Changed the type (to unsigned) of a couple of variables.
* Returned earlier when possible to reduce indentation.
* Used platform_get_irq_optional() instead of platform_get_irq() to avoid
a useless warning.
* Handled probe deferral correctly.
* Applied a massive s/nfc/nandc/ as suggested by Geert to avoid
confusions with the near-field-communication device.
* Mentioned Evatronix as original authors of the IP in the commit log and
in the header.
* Added an additional check on the validity of the child nodes reg property.
* A couple of style fixes.
Miquel Raynal (4):
dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
mtd: rawnand: rzn1: Add new NAND controller driver
MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller
ARM: dts: r9a06g032: Describe NAND controller
.../mtd/renesas,rzn1-nand-controller.yaml | 64 +
MAINTAINERS | 7 +
arch/arm/boot/dts/r9a06g032.dtsi | 12 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/rzn1-nand-controller.c | 1422 +++++++++++++++++
6 files changed, 1512 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml
create mode 100644 drivers/mtd/nand/raw/rzn1-nand-controller.c
--
2.27.0
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^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
@ 2021-12-16 13:41 ` Geert Uytterhoeven
2021-12-16 13:43 ` Geert Uytterhoeven
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:41 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Sagar Kadam, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Pratyush Yadav, Michael Walle,
linux-mtd
Cc: linux-kernel, devicetree, linux-riscv, Miquel Raynal,
linux-renesas-soc, Magnus Damm, Gareth Williams, Phil Edworthy,
Geert Uytterhoeven, Thomas Petazzoni, Milan Stevanovic,
Jimmy Lalande
From: Miquel Raynal <miquel.raynal@bootlin.com>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND
controller.
This time the driver has been tested with a fully-upstream device tree
on top of a v5.16-rc4. The DT used is very close to the r9a06g032-db.
Cheers,
Miquèl
Changes in v4:
* Set unevaluatedProperties set to false in the bindings.
* Change the clock names by removing the nand_ prefix which is
redundant, even though the clocks are named like this in the spec. The
name remains clear enough anyway.
Changes in v3:
* Rebased on top of a fully-upstream recent kernel.
* Renamed the clocks in the bindings and the driver to match the
documentation (lower-cased): nand_hclk & nand_eclk.
* Added a new commit describing the NAND controller in the r9a06g032
DTSI.
* Added the Reviewed-by and Tested-by tags received.
Changes in v2:
* Added the family-specific rzn1 compatible as suggested by Geert.
Updated the bindings, the binding file name, the compatible used in
the driver, the MAINTAINERS entry, etc.
* Added an ARCH_RENESAS Kconfig dependency.
* Changed the type (to unsigned) of a couple of variables.
* Returned earlier when possible to reduce indentation.
* Used platform_get_irq_optional() instead of platform_get_irq() to avoid
a useless warning.
* Handled probe deferral correctly.
* Applied a massive s/nfc/nandc/ as suggested by Geert to avoid
confusions with the near-field-communication device.
* Mentioned Evatronix as original authors of the IP in the commit log and
in the header.
* Added an additional check on the validity of the child nodes reg property.
* A couple of style fixes.
Miquel Raynal (4):
dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
mtd: rawnand: rzn1: Add new NAND controller driver
MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller
ARM: dts: r9a06g032: Describe NAND controller
.../mtd/renesas,rzn1-nand-controller.yaml | 64 +
MAINTAINERS | 7 +
arch/arm/boot/dts/r9a06g032.dtsi | 12 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/rzn1-nand-controller.c | 1422 +++++++++++++++++
6 files changed, 1512 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml
create mode 100644 drivers/mtd/nand/raw/rzn1-nand-controller.c
--
2.27.0
_______________________________________________
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^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
@ 2021-12-16 13:43 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
` (2 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:43 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Anup Patel, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Pratyush Yadav, Michael Walle,
linux-mtd
Cc: linux-kernel, devicetree, linux-riscv, Miquel Raynal,
linux-renesas-soc, Magnus Damm, Gareth Williams, Phil Edworthy,
Geert Uytterhoeven, Thomas Petazzoni, Milan Stevanovic,
Jimmy Lalande
From: Miquel Raynal <miquel.raynal@bootlin.com>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND
controller.
This time the driver has been tested with a fully-upstream device tree
on top of a v5.16-rc4. The DT used is very close to the r9a06g032-db.
Cheers,
Miquèl
Changes in v4:
* Set unevaluatedProperties set to false in the bindings.
* Change the clock names by removing the nand_ prefix which is
redundant, even though the clocks are named like this in the spec. The
name remains clear enough anyway.
Changes in v3:
* Rebased on top of a fully-upstream recent kernel.
* Renamed the clocks in the bindings and the driver to match the
documentation (lower-cased): nand_hclk & nand_eclk.
* Added a new commit describing the NAND controller in the r9a06g032
DTSI.
* Added the Reviewed-by and Tested-by tags received.
Changes in v2:
* Added the family-specific rzn1 compatible as suggested by Geert.
Updated the bindings, the binding file name, the compatible used in
the driver, the MAINTAINERS entry, etc.
* Added an ARCH_RENESAS Kconfig dependency.
* Changed the type (to unsigned) of a couple of variables.
* Returned earlier when possible to reduce indentation.
* Used platform_get_irq_optional() instead of platform_get_irq() to avoid
a useless warning.
* Handled probe deferral correctly.
* Applied a massive s/nfc/nandc/ as suggested by Geert to avoid
confusions with the near-field-communication device.
* Mentioned Evatronix as original authors of the IP in the commit log and
in the header.
* Added an additional check on the validity of the child nodes reg property.
* A couple of style fixes.
Miquel Raynal (4):
dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
mtd: rawnand: rzn1: Add new NAND controller driver
MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller
ARM: dts: r9a06g032: Describe NAND controller
.../mtd/renesas,rzn1-nand-controller.yaml | 64 +
MAINTAINERS | 7 +
arch/arm/boot/dts/r9a06g032.dtsi | 12 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/rzn1-nand-controller.c | 1422 +++++++++++++++++
6 files changed, 1512 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml
create mode 100644 drivers/mtd/nand/raw/rzn1-nand-controller.c
--
2.27.0
_______________________________________________
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
2021-12-16 13:43 ` Geert Uytterhoeven
@ 2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:47 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Pratyush Yadav, Michael Walle,
MTD Maling List
Cc: Rob Herring, Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
Conor Dooley, linux-riscv,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Miquel Raynal, Linux-Renesas, Magnus Damm, Gareth Williams,
Phil Edworthy, Thomas Petazzoni, Milan Stevanovic, Jimmy Lalande
On Thu, Dec 16, 2021 at 2:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> From: Miquel Raynal <miquel.raynal@bootlin.com>
>
> Hello,
>
> Here is a short series bringing support for Renesas RZ/N1 NAND
> controller.
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
` (2 preceding siblings ...)
2021-12-16 13:47 ` Geert Uytterhoeven
@ 2021-12-16 13:48 ` Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:48 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Sagar Kadam, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Pratyush Yadav, Michael Walle,
MTD Maling List
Cc: Linux Kernel Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, Miquel Raynal, Linux-Renesas, Magnus Damm,
Gareth Williams, Phil Edworthy, Thomas Petazzoni,
Milan Stevanovic, Jimmy Lalande
On Thu, Dec 16, 2021 at 2:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> From: Miquel Raynal <miquel.raynal@bootlin.com>
>
> Hello,
>
> Here is a short series bringing support for Renesas RZ/N1 NAND
> controller.
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
` (3 preceding siblings ...)
2021-12-16 13:48 ` Geert Uytterhoeven
@ 2021-12-16 13:48 ` Geert Uytterhoeven
4 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2021-12-16 13:48 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring, Palmer Dabbelt,
Paul Walmsley, Anup Patel, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Pratyush Yadav, Michael Walle,
MTD Maling List
Cc: Linux Kernel Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, Miquel Raynal, Linux-Renesas, Magnus Damm,
Gareth Williams, Phil Edworthy, Thomas Petazzoni,
Milan Stevanovic, Jimmy Lalande
On Thu, Dec 16, 2021 at 2:44 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> From: Miquel Raynal <miquel.raynal@bootlin.com>
>
> Hello,
>
> Here is a short series bringing support for Renesas RZ/N1 NAND
> controller.
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 40+ messages in thread