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[209.85.219.174]) by smtp.gmail.com with ESMTPSA id h7-20020a05620a400700b006b945519488sm99116qko.88.2022.10.03.23.42.05 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Oct 2022 23:42:05 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id 203so15683313ybc.10 for ; Mon, 03 Oct 2022 23:42:05 -0700 (PDT) X-Received: by 2002:a25:bc8f:0:b0:6bd:ab73:111 with SMTP id e15-20020a25bc8f000000b006bdab730111mr8977272ybk.36.1664865724940; Mon, 03 Oct 2022 23:42:04 -0700 (PDT) MIME-Version: 1.0 References: <20221003223222.448551-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221003223222.448551-2-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221003223222.448551-2-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 4 Oct 2022 08:41:53 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller To: Prabhakar Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Magnus Damm , Heiko Stuebner , Guo Ren , Conor Dooley , Philipp Tomsich , Nathan Chancellor , Atish Patra , Anup Patel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221003_234209_303761_882A0895 X-CRM114-Status: GOOD ( 22.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Prabhakar, On Tue, Oct 4, 2022 at 12:32 AM Prabhakar wrote: > From: Lad Prabhakar > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > describes the L2 cache block. > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml Not andestech,ax45mp-cache.yaml? > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive L2 Cache Controller Andestech AX45MP? > + > +maintainers: > + - Lad Prabhakar > + > +description: > + A level-2 cache (L2C) is used to improve the system performance by providing > + a larger amount of cache line entries and reasonable access delays. The L2C > + is shared between cores, and a non-inclusive non-exclusive policy is used. > + > +properties: > + compatible: > + items: > + - const: andestech,ax45mp-cache > + - const: cache This makes the schema apply to any node which is compatible with "cache", cfr. the report from Rob's bot. You need a select block to avoid that, cfr. Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv