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[209.85.219.182]) by smtp.gmail.com with ESMTPSA id bm34-20020a05620a19a200b006cbd92ca141sm13974969qkb.133.2022.10.04.02.12.45 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Oct 2022 02:12:45 -0700 (PDT) Received: by mail-yb1-f182.google.com with SMTP id 63so16074959ybq.4 for ; Tue, 04 Oct 2022 02:12:45 -0700 (PDT) X-Received: by 2002:a5b:104:0:b0:6b0:429:3fe9 with SMTP id 4-20020a5b0104000000b006b004293fe9mr24038304ybx.543.1664874764897; Tue, 04 Oct 2022 02:12:44 -0700 (PDT) MIME-Version: 1.0 References: <20221003223222.448551-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221003223222.448551-2-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 4 Oct 2022 11:12:32 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller To: "Lad, Prabhakar" Cc: Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Magnus Damm , Heiko Stuebner , Guo Ren , Philipp Tomsich , Nathan Chancellor , Atish Patra , Anup Patel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221004_021249_692796_6A472439 X-CRM114-Status: GOOD ( 36.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Prabhakar, On Tue, Oct 4, 2022 at 9:59 AM Lad, Prabhakar wrote: > On Tue, Oct 4, 2022 at 8:32 AM Conor Dooley wrote: > > On Tue, Oct 04, 2022 at 08:26:01AM +0100, Lad, Prabhakar wrote: > > > On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven wrote: > > > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar wrote: > > > > > From: Lad Prabhakar > > > > > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > > > describes the L2 cache block. > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > Thanks for your patch! > > > > > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > > > > > > > Not andestech,ax45mp-cache.yaml? > > > > > > > I wasn't sure as we were including this in soc/renesas so named it as > > > r9a07g043f-l2-cache.yaml if there are no issues I'll rename it > > > andestech,ax45mp-cache.yaml. > > > > I may be guilty of suggesting soc/renesas in the first place, but should > > this maybe be in soc/andestech? I have no skin in the game, so at the > > end of the day it doesnt matter to me, but I would imagine that you're > > not going to be the only users of this l2 cache? Or is it a case of "we > > will deal with future users when said future users arrive"? But either > > way, naming it after the less specific compatible makes more sense to > > me. > > > As there aren't any Andestech SoCs upstream, I am in favour of keeping > in soc/renesas for maintenance. If in future there comes a new soc > from Andestech (which will go into soc/andestech) we will have to > split the maintenance work. > But anyway if there will be any users of L2 cache we could always > provide a config option which can be used by other SoCs. What about Documentation/devicetree/bindings/cache/? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv