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Tue, 02 Dec 2025 09:33:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IG179kyf4Mm4EZn9RyKrnN/DxnneyLSsedMspzlE6CZ3Ky4wwtL8+2G/uOMzpk2ZH6Ndd7dM7KovwJMOMXT4d4= X-Received: by 2002:a05:7301:9c91:b0:2a4:4f86:822a with SMTP id 5a478bee46e88-2a941887a80mr12870574eec.33.1764696786411; Tue, 02 Dec 2025 09:33:06 -0800 (PST) MIME-Version: 1.0 References: <20251020-proc_status-v1-1-59d2c8ccd4f0@rivosinc.com> <418119d5-4892-4697-a0ab-6a76302fea77@canonical.com> <22b5f8d0-c2c1-4072-b311-5750c8c6a045@canonical.com> In-Reply-To: <22b5f8d0-c2c1-4072-b311-5750c8c6a045@canonical.com> From: Valentin Haudiquet Date: Tue, 2 Dec 2025 18:32:54 +0100 X-Gm-Features: AWmQ_blrzMcFMK1lQ3N7zx2u_eMkcnC08x_E3cyCK8g9mRec8_cl7vSSpI94IL4 Message-ID: Subject: Re: [PATCH RFC] arch/riscv: add proc status (proc//status) To: Heinrich Schuchardt Cc: Deepak Gupta , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, alexghiti@rivosinc.com, cleger@rivosinc.com, zong.li@sifive.com, jesse.huang@sifive.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251202_093312_748622_02F3BA13 X-CRM114-Status: GOOD ( 35.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Tested-by: Valentin Haudiquet On Thu, 23 Oct 2025 at 10:11, Heinrich Schuchardt wrote: > > On 10/23/25 01:38, Deepak Gupta wrote: > > Hi Hienrich, > > > > > > On Tue, Oct 21, 2025 at 01:13:36PM +0200, Heinrich Schuchardt wrote: > >> On 10/20/25 20:18, Deepak Gupta wrote: > >>> x86 has proc//status to see various runtime characteristics > >>> of running task. Implement same for riscv. This patch implements > >>> status for shadow stack and landing pad state. > >>> > >>> Signed-off-by: Deepak Gupta > >>> --- > >>> This is just a one patch but sending it as RFC with cover letter to seek > >>> feedback. x86 has `arch_proc_pid_thread_features` to enumerate status of > >>> arch thread specific features on runtime. This can be done using prctl > >>> as well but from quick/script perspective `cat /proc//status` is > >>> more > >>> desirable. In this patch, simply `arch_proc_pid_thread_features` is > >>> implemented > >>> for riscv which queries shadow stack and landing pad state and > >>> reports back. > >>> Thus it is dependent on riscv user cfi enabling series. > >> > >> Hello Deepak, > >> > >> This looks like a valuable addition. > >> > >> Shouldn't architecture specific fields be in > >> /proc//arch_status and not in /proc//status? > > > > Just following what x86 did. I believe shadow stack and landing pad are > > there > > in arm64, x86 and riscv. So probably /proc//status is best place. > >> > >> Please, add a documentation patch adding the RISC-V specific fields to > >> "3.12 /proc//arch_status - Task architecture specific information" > >> in Documentation/filesystems/proc.rst. > >> > >> Should you stick to /proc/*/status, please, add the documentation to > >> Documentation/arch/riscv/. > > > > Will do. > > > >> > >>> > >>> If this patch itself is self-standing and good enough, I can roll > >>> this patch > >>> as part of riscv user cfi enabling series. > >>> > >>> OR > >>> > >>> If there is ask for other riscv thread specific features that could be > >>> enumerated in similar fashion, we will need it to be done as separate > >>> series > >>> (with `thread_features` added to `thread_info`) > >>> > >>> Example output below. > >>> > >>> Name: cat > >>> Umask: 0022 > >>> State: R (running) > >>> Tgid: 133 > >>> Ngid: 0 > >>> Pid: 133 > >>> PPid: 129 > >>> TracerPid: 0 > >>> Uid: 0 0 0 0 > >>> Gid: 0 0 0 0 > >>> FDSize: 256 > >>> Groups: 0 10 > >>> NStgid: 133 > >>> NSpid: 133 > >>> NSpgid: 133 > >>> NSsid: 129 > >>> Kthread: 0 > >>> VmPeak: 10788 kB > >>> VmSize: 10788 kB > >>> VmLck: 0 kB > >>> VmPin: 0 kB > >>> VmHWM: 1400 kB > >>> VmRSS: 1400 kB > >>> RssAnon: 116 kB > >>> RssFile: 1284 kB > >>> RssShmem: 0 kB > >>> VmData: 92 kB > >>> VmStk: 8324 kB > >>> VmExe: 4 kB > >>> VmLib: 2312 kB > >>> VmPTE: 40 kB > >>> VmSwap: 0 kB > >>> HugetlbPages: 0 kB > >>> CoreDumping: 0 > >>> THP_enabled: 0 > >>> untag_mask: 0xffffffffffffffff > >>> Threads: 1 > >>> SigQ: 0/31771 > >>> SigPnd: 0000000000000000 > >>> ShdPnd: 0000000000000000 > >>> SigBlk: 0000000000000000 > >>> SigIgn: 0000000000000000 > >>> SigCgt: 0000000000000000 > >>> CapInh: 0000000000000000 > >>> CapPrm: 000001ffffffffff > >>> CapEff: 000001ffffffffff > >>> CapBnd: 000001ffffffffff > >>> CapAmb: 0000000000000000 > >>> NoNewPrivs: 0 > >>> Seccomp: 0 > >>> Seccomp_filters: 0 > >>> Speculation_Store_Bypass: unknown > >>> SpeculationIndirectBranch: unsupported > >>> Cpus_allowed: 3 > >>> Cpus_allowed_list: 0-1 > >>> Mems_allowed: 1 > >>> Mems_allowed_list: 0 > >>> voluntary_ctxt_switches: 0 > >>> nonvoluntary_ctxt_switches: 3 > >>> riscv_thread_features: shstk_enabled lpad_enabled > >>> riscv_thread_features_locked: shstk_unlocked lpad_unlocked > >>> --- > >>> arch/riscv/kernel/Makefile | 1 + > >>> arch/riscv/kernel/cpu/Makefile | 1 + > >>> arch/riscv/kernel/cpu/proc.c | 28 ++++++++++++++++++++++++++++ > >>> 3 files changed, 30 insertions(+) > >>> > >>> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > >>> index f60fce69b725..b32c11667d81 100644 > >>> --- a/arch/riscv/kernel/Makefile > >>> +++ b/arch/riscv/kernel/Makefile > >>> @@ -71,6 +71,7 @@ obj-y += vendor_extensions.o > >>> obj-y += vendor_extensions/ > >>> obj-y += probes/ > >>> obj-y += tests/ > >>> +obj-y += cpu/ > >>> obj-$(CONFIG_MMU) += vdso.o vdso/ > >>> obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o > >>> diff --git a/arch/riscv/kernel/cpu/Makefile b/arch/riscv/kernel/cpu/ > >>> Makefile > >>> new file mode 100644 > >>> index 000000000000..2b474fb49afe > >>> --- /dev/null > >>> +++ b/arch/riscv/kernel/cpu/Makefile > >>> @@ -0,0 +1 @@ > >>> +obj-$(CONFIG_PROC_FS) += proc.o > >>> diff --git a/arch/riscv/kernel/cpu/proc.c b/arch/riscv/kernel/cpu/proc.c > >>> new file mode 100644 > >>> index 000000000000..4661190c43d1 > >>> --- /dev/null > >>> +++ b/arch/riscv/kernel/cpu/proc.c > >>> @@ -0,0 +1,28 @@ > >>> +// SPDX-License-Identifier: GPL-2.0 > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> + > >>> +#ifdef CONFIG_RISCV_USER_CFI > >>> + > >>> +void arch_proc_pid_thread_features(struct seq_file *m, struct > >>> task_struct *task) > >>> +{ > >>> + seq_puts(m, "riscv_thread_features:\t"); > >>> + if (is_shstk_enabled(task)) > >>> + seq_puts(m, "shstk_enabled "); > >> > >> According to Documentation/arch/x86/shstk.rst, x86 is avoiding the > >> '_enabled' postfix here: > >> > >> x86_Thread_features: shstk wrss > > > > I can follow same and use `shstk`. We don't have `wrss` because > > shadow stack is writeable by right instruction (sspush and ssamoswap) in > > riscv. > > > >> > >>> + > >>> + if (is_indir_lp_enabled(task)) > >>> + seq_puts(m, "lpad_enabled "); > > > > Would you prefer similar here. Just "lpad"? > > That would be consistent with what is done for x86. > > Best regards > > Heinrich > > > > >>> + > >>> + seq_putc(m, '\n'); > >>> + > >>> + seq_puts(m, "riscv_thread_features_locked:\t"); > >>> + is_shstk_locked(task) ? seq_puts(m, "shstk_locked ") : > >>> seq_puts(m, "shstk_unlocked "); > >>> + is_indir_lp_locked(task) ? seq_puts(m, "lpad_locked ") : > >>> seq_puts(m, "lpad_unlocked "); > >> > >> Why do we need any entry for an unlocked feature in > >> riscv_thread_features_locked? > > > > absence of "feature_locked" is considered unlocked, then I can drop it. > > > >> > >> Best regards > >> > >> Heinrich > >> > >>> + seq_putc(m, '\n'); > >>> +} > >>> +#endif /* CONFIG_RISCV_USER_CFI */ > >>> > >>> --- > >>> base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787 > >>> change-id: 20251017-proc_status-df1aedc85c7c > >>> -- > >>> - debug > >>> > >> > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv