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Tue, 06 May 2025 02:24:34 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:d5f0:7802:c94b:10f6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441b8992b4csm165890855e9.0.2025.05.06.02.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 02:24:34 -0700 (PDT) Mime-Version: 1.0 Date: Tue, 06 May 2025 11:24:33 +0200 Message-Id: Subject: Re: [PATCH 0/5] Enable hstateen bits lazily for the KVM RISC-V Guests Cc: , , , , "linux-riscv" To: "Atish Patra" , "Anup Patel" , "Atish Patra" , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250506_022437_040677_CE7AFA6A X-CRM114-Status: GOOD ( 14.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org 2025-05-05T14:39:25-07:00, Atish Patra : > This series adds support for enabling hstateen bits lazily at runtime > instead of statically at bootime. The boot time enabling happens for > all the guests if the required extensions are present in the host and/or > guest. That may not be necessary if the guest never exercise that > feature. We can enable the hstateen bits that controls the access lazily > upon first access. This providers KVM more granular control of which > feature is enabled in the guest at runtime. > > Currently, the following hstateen bits are supported to control the access > from VS mode. > > 1. BIT(58): IMSIC : STOPEI and IMSIC guest interrupt file > 2. BIT(59): AIA : SIPH/SIEH/STOPI > 3. BIT(60): AIA_ISEL : Indirect csr access via siselect/sireg > 4. BIT(62): HSENVCFG : SENVCFG access > 5. BIT(63): SSTATEEN0 : SSTATEEN0 access > > KVM already support trap/enabling of BIT(58) and BIT(60) in order > to support sw version of the guest interrupt file. I don't think KVM toggles the hstateen bits at runtime, because that would mean there is a bug even in current KVM. > This series extends > those to enable to correpsonding hstateen bits in PATCH1. The remaining > patches adds lazy enabling support of the other bits. The ISA has a peculiar design for hstateen/sstateen interaction: For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in sstateen when accessed in VS-mode. This means we must clear bit 63 in hstateen and trap on sstateen accesses if any of the sstateen bits are not supposed to be read-only 0 to the guest while the hypervisor wants to have them as 0. Thanks. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv