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Tue, 24 Jun 2025 05:40:38 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:b00d:6d5f:6e67:f5e8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4536fefd2b4sm83300675e9.36.2025.06.24.05.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 05:40:38 -0700 (PDT) Mime-Version: 1.0 Date: Tue, 24 Jun 2025 14:40:37 +0200 Message-Id: Subject: Re: [PATCH v2 0/2] RISC-V: turn sbi_ecall into a variadic macro Cc: , , "Paul Walmsley" , , "Alexandre Ghiti" , "Atish Patra" , , , , To: "David Laight" , "Palmer Dabbelt" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250619190315.2603194-1-rkrcmar@ventanamicro.com> <20250624090923.5521a0f2@pumpkin> In-Reply-To: <20250624090923.5521a0f2@pumpkin> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250624_054041_185167_7AB6C4AF X-CRM114-Status: GOOD ( 14.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org 2025-06-24T09:09:23+01:00, David Laight : > On Mon, 23 Jun 2025 15:53:58 -0700 (PDT) > Palmer Dabbelt wrote: >> On Thu, 19 Jun 2025 12:03:12 PDT (-0700), rkrcmar@ventanamicro.com wrote: >> > v2 has a completely rewritten [1/2], and fixes some missed trailing >> > zeroes in [2/2]. The fixes in [2/2] are important for v2, because >> > sbi_ecall doesn't fill the registers with zeroes anymore. >> >> The SBI spec says "Registers that are not defined in the SBI function >> call are not reserved." and I'm not really sure what to make of that. At the beginning, SBI says that only a0-a5 can contain ecall arguments, and then each function indirectly says which registers actually contain arguments. a0-a5 that don't contain arguments are not reserved, just like all the other unspecified registers. >> Specifically: does that mean implementations are allowed to ascribe >> custom meaning to those parameters and might start doing stuff if >> they're not set to zero? SBI explicitly reserves registers if they are intended to be used in the future. The result of the ecall must be exactly the same regardless of the value in unspecified (not reserved) registers. We can't really tell what an SBI implementation will do with unspecified registers, but the most sane thing would be to ignore them. > Or does it mean they aren't guaranteed to be preserved? No, they are preserved: "All registers except a0 & a1 must be preserved across an SBI call by the callee." _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv