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boundary="===============8851475887892565863==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============8851475887892565863== Content-Type: multipart/signed; boundary=98c1991e3a84cabccc87599576fe5533e92c3b07b62de26e2101639d3652; micalg=pgp-sha512; protocol="application/pgp-signature" Content-Transfer-Encoding: 8bit --98c1991e3a84cabccc87599576fe5533e92c3b07b62de26e2101639d3652 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Wed, Sep 09, 2026 at 03:51:02PM +0800, Inochi Amaoto wrote: > [...] > > > > +static int k3_pcie_parse_port(struct k1_pcie *k1) > > > +{ > > > + u32 status0, status1, status2; > > > + > > > + /* This register require a RAW for cleanup */ > > > + status0 =3D readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); > > > + status1 =3D readl_relaxed(k1->link + INTR_STATUS); > > > + status2 =3D readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); > > > + > > > + writel_relaxed(status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); > > > + writel_relaxed(status1, k1->link + INTR_STATUS); > > > + writel_relaxed(status2, k1->link + K3_ADDR_INTR_STATUS1); > > > + > > > + return k1_pcie_parse_port(k1); > > > +} > > > + > > > > Are these status registers accessible before the controller clocks are = enabled > > and resets released? k3_pcie_parse_port() runs before dw_pcie_host_init= (), which > > calls k3_pcie_init() to enable those resources. > > > > Yes they can. It is something interesting. > > > The SDK uses the same ordering, but I am not sure whether it relies on = firmware > > leaving the registers accessible. If so, would it be safer to move this= clearing > > into k3_pcie_init(), after enabling the resources? > > > > In fact, I have no idea about which clock control this MMIO area, if it i= s dbi > clock (but I guest it is not), it is kind of weird for this clear and sho= uld > move to the init. Do you have some knowledge on this? I checked with our hardware team. PMU AP and PCIECFG share a system clock derived from PLL1 /8 or /6. This clock is already available during early boot, before PCIe controller initialization. The register accesses in k3_pcie_parse_port() therefore do not need to wait for k3_pcie_init(). That resolves my concern about the ordering. - Troy --98c1991e3a84cabccc87599576fe5533e92c3b07b62de26e2101639d3652 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iIMEABYKACsWIQSL4Ay2cExaPXAQcU2YCe+A+TM0LwUCaqoNyA0caUB0cm95LXku b3JnAAoJEJgJ74D5MzQvlUkBANa2w+Z52VSTg6VPhIdnN5L53HC35mTROdqQpRPi nqx2AP4rMeIb5iWf85lMB8tpSZ2nnHapBGg95rVgzpbj5/TeBg== =gkSx -----END PGP SIGNATURE----- --98c1991e3a84cabccc87599576fe5533e92c3b07b62de26e2101639d3652-- --===============8851475887892565863== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============8851475887892565863==--