From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com,
"Vincent Chen" <vincent.chen@sifive.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Heiko Stuebner" <heiko@sntech.de>, "Guo Ren" <guoren@kernel.org>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Wenting Zhang" <zephray@outlook.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Xianting Tian" <xianting.tian@linux.alibaba.com>,
"David Hildenbrand" <david@redhat.com>,
"Al Viro" <viro@zeniv.linux.org.uk>,
"Andrew Bresticker" <abrestic@rivosinc.com>
Subject: Re: [PATCH -next v14 13/19] riscv: signal: Add sigcontext save/restore for vector
Date: Wed, 1 Mar 2023 18:27:31 +0000 [thread overview]
Message-ID: <Y/+ZE1j2usg5C1Uv@spud> (raw)
In-Reply-To: <20230224170118.16766-14-andy.chiu@sifive.com>
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On Fri, Feb 24, 2023 at 05:01:12PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> This patch facilitates the existing fp-reserved words for placement of
> the first extension's context header on the user's sigframe. A context
> header consists of a distinct magic word and the size, including the
> header itself, of an extension on the stack. Then, the frame is followed
> by the context of that extension, and then a header + context body for
> another extension if exists. If there is no more extension to come, then
> the frame must be ended with a null context header. A special case is
> rv64gc, where the kernel support no extensions requiring to expose
> additional regfile to the user. In such case the kernel would place the
> null context header right after the first reserved word of
> __riscv_q_ext_state when saving sigframe. And the kernel would check if
> all reserved words are zeros when a signal handler returns.
>
> __riscv_q_ext_state---->| |<-__riscv_extra_ext_header
> ~ ~
> .reserved[0]--->|0 |<- .reserved
> <-------|magic |<- .hdr
> | |size |_______ end of sc_fpregs
> | |ext-bdy|
> | ~ ~
> +)size ------->|magic |<- another context header
> |size |
> |ext-bdy|
> ~ ~
> |magic:0|<- null context header
> |size:0 |
>
> The vector registers will be saved in datap pointer. The datap pointer
> will be allocated dynamically when the task needs in kernel space. On
> the other hand, datap pointer on the sigframe will be set right after
> the __riscv_v_ext_state data structure.
>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Suggested-by: Vineet Gupta <vineetg@rivosinc.com>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> +static long save_v_state(struct pt_regs *regs, void **sc_vec)
> +{
> + /*
> + * Put __sc_riscv_v_state to the user's signal context space pointed
> + * by sc_vec and the datap point the address right
> + * after __sc_riscv_v_state.
> + */
AFAIU, this comment describes the assignments here. I think it would be
significantly clearer if you defined the variables here & moved the
assignment and comment further down the function.
> + struct __riscv_ctx_hdr __user *hdr = (struct __riscv_ctx_hdr *)(*sc_vec);
> + struct __sc_riscv_v_state __user *state = (struct __sc_riscv_v_state *)(hdr + 1);
> + void __user *datap = state + 1;
> + long err;
> +
> + /* datap is designed to be 16 byte aligned for better performance */
> + WARN_ON(unlikely(!IS_ALIGNED((unsigned long)datap, 16)));
> +
> + riscv_v_vstate_save(current, regs);
> + /* Copy everything of vstate but datap. */
> + err = __copy_to_user(&state->v_state, ¤t->thread.vstate,
> + offsetof(struct __riscv_v_ext_state, datap));
> + /* Copy the pointer datap itself. */
> + err |= __put_user(datap, &state->v_state.datap);
> + /* Copy the whole vector content to user space datap. */
> + err |= __copy_to_user(datap, current->thread.vstate.datap, riscv_v_vsize);
> + /* Copy magic to the user space after saving all vector conetext */
> + err |= __put_user(RISCV_V_MAGIC, &hdr->magic);
> + err |= __put_user(riscv_v_sc_size, &hdr->size);
> + if (unlikely(err))
> + return err;
> +
> + /* Only progress the sv_vec if everything has done successfully */
> + *sc_vec += riscv_v_sc_size;
> + return 0;
> +}
> static long restore_sigcontext(struct pt_regs *regs,
> struct sigcontext __user *sc)
> {
> + void *sc_ext_ptr = &sc->sc_extdesc.hdr;
> + __u32 rsvd;
> long err;
> - size_t i;
> -
> /* sc_regs is structured the same as the start of pt_regs */
> err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs));
> if (unlikely(err))
> - return err;
> + goto done;
> /* Restore the floating-point state. */
> if (has_fpu()) {
> err = restore_fp_state(regs, &sc->sc_fpregs);
> if (unlikely(err))
> - return err;
> + goto done;
> }
>
> - /* We support no other extension state at this time. */
> - for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) {
> - u32 value;
> -
> - err = __get_user(value, &sc->sc_fpregs.q.reserved[i]);
> - if (unlikely(err))
> + /* Check the reserved word before extensions parsing */
> + err = __get_user(rsvd, &sc->sc_extdesc.reserved);
> + if (unlikely(err))
> + goto done;
> + if (unlikely(rsvd))
> + goto invalid;
> +
> + while (1 && !err) {
This is just while (!err), no?
> + __u32 magic, size;
> + struct __riscv_ctx_hdr *head = (struct __riscv_ctx_hdr *)sc_ext_ptr;
> +
> + err |= __get_user(magic, &head->magic);
> + err |= __get_user(size, &head->size);
> + if (err)
> + goto done;
> +
> + sc_ext_ptr += sizeof(struct __riscv_ctx_hdr);
> + switch (magic) {
> + case END_MAGIC:
> + if (size != END_HDR_SIZE)
> + goto invalid;
> + goto done;
> + case RISCV_V_MAGIC:
> + if (!has_vector() || !riscv_v_vstate_query(regs))
> + goto invalid;
> + if (size != riscv_v_sc_size)
> + goto invalid;
> + err = __restore_v_state(regs, sc_ext_ptr);
> break;
> - if (value != 0)
> - return -EINVAL;
> + default:
> + goto invalid;
Why does this need a goto, rather than returning -EINVAL directly?
> + }
> + sc_ext_ptr = ((void *)(head) + size);
> }
> +done:
> return err;
> +invalid:
> + return -EINVAL;
> +}
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next prev parent reply other threads:[~2023-03-01 18:27 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 17:00 [PATCH -next v14 00/19] riscv: Add vector ISA support Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-02-28 21:56 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-02-28 22:07 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-02-28 22:31 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-02-28 22:17 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-02-28 22:36 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-02-28 22:38 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-02-28 23:00 ` Conor Dooley
2023-03-15 4:00 ` Andy Chiu
2023-03-02 11:12 ` Björn Töpel
2023-03-15 4:05 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 09/19] riscv: Add task switch support for vector Andy Chiu
2023-03-01 16:41 ` Conor Dooley
2023-03-01 16:57 ` Björn Töpel
2023-03-02 11:07 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-01 16:53 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 11/19] riscv: Add ptrace vector support Andy Chiu
2023-03-01 17:29 ` Conor Dooley
2023-03-02 11:27 ` Björn Töpel
2023-03-14 10:39 ` Andy Chiu
2023-03-14 10:44 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-01 17:56 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-01 18:27 ` Conor Dooley [this message]
2023-03-02 12:42 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-01 19:21 ` Conor Dooley
2023-03-02 12:47 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-01 21:00 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-01 21:34 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-01 21:38 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-02-24 21:35 ` kernel test robot
2023-02-25 1:33 ` kernel test robot
2023-03-01 18:00 ` Nathan Chancellor
2023-03-01 18:44 ` Conor Dooley
2023-02-25 8:28 ` kernel test robot
2023-02-27 10:18 ` Conor Dooley
2023-02-27 13:40 ` Darius Rad
2023-02-27 13:58 ` Conor Dooley
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