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X-IronPort-AV: E=Sophos;i="5.97,315,1669100400"; d="asc'?scan'208";a="212990992" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 21 Feb 2023 08:11:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 21 Feb 2023 08:11:04 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 08:11:01 -0700 Date: Tue, 21 Feb 2023 15:10:35 +0000 From: Conor Dooley To: Hal Feng CC: , , , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Ben Dooks , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Emil Renner Berthing , Subject: Re: [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Message-ID: References: <20230221024645.127922-1-hal.feng@starfivetech.com> <20230221024645.127922-17-hal.feng@starfivetech.com> MIME-Version: 1.0 In-Reply-To: <20230221024645.127922-17-hal.feng@starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230221_071131_672781_94887116 X-CRM114-Status: GOOD ( 13.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5711480393226082370==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============5711480393226082370== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="r8mdfKzrJCh2QVlz" Content-Disposition: inline --r8mdfKzrJCh2QVlz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Feb 21, 2023 at 10:46:42AM +0800, Hal Feng wrote: > Add a new compatible string in cpu.yaml for SiFive S7 CPU > core which is used on SiFive U74-MC core complex etc. >=20 > Signed-off-by: Hal Feng Reviewed-by: Conor Dooley > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Document= ation/devicetree/bindings/riscv/cpus.yaml > index a2884e3113da..54bfe24a436b 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -35,6 +35,7 @@ properties: > - sifive,e7 > - sifive,e71 > - sifive,rocket0 > + - sifive,s7 > - sifive,u5 > - sifive,u54 > - sifive,u7 > --=20 > 2.38.1 >=20 >=20 --r8mdfKzrJCh2QVlz Content-Type: application/pgp-signature; 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