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27 Feb 2023 04:57:18 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 27 Feb 2023 04:57:16 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16 via Frontend Transport; Mon, 27 Feb 2023 04:57:15 -0700 Date: Mon, 27 Feb 2023 11:56:48 +0000 From: Conor Dooley To: Song Shuai CC: , , , , , , , , Subject: Re: [PATCH] sched/doc: supplement CPU capacity with RISC-V Message-ID: References: <20230227105941.2749193-1-suagrfillet@gmail.com> MIME-Version: 1.0 In-Reply-To: <20230227105941.2749193-1-suagrfillet@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230227_115727_854696_1E1A8CA4 X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1929429015146575580==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============1929429015146575580== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Qu+vqTjLVyvhigH7" Content-Disposition: inline --Qu+vqTjLVyvhigH7 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Feb 27, 2023 at 06:59:41PM +0800, Song Shuai wrote: > This commit 7d2078310cbf ("dt-bindings: arm: move cpu-capacity to a > shared loation") updates some references about capacity-dmips-mhz Not requesting a respin for this, but mentioning commit 991994509ee9 ("dt-bindings: riscv: add a capacity-dmips-mhz cpu property") is probably more relevant as a justification for this change. > property in this document. >=20 > The list of architectures using capacity-dmips-mhz omits RISC-V, so > supplements it here. >=20 > Signed-off-by: Song Shuai > --- > Documentation/scheduler/sched-capacity.rst | 2 +- > Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/s= cheduler/sched-capacity.rst > index 8e2b8538bc2b..e2c1cf743158 100644 > --- a/Documentation/scheduler/sched-capacity.rst > +++ b/Documentation/scheduler/sched-capacity.rst > @@ -258,7 +258,7 @@ Linux cannot currently figure out CPU capacity on its= own, this information thus > needs to be handed to it. Architectures must define arch_scale_cpu_capac= ity() > for that purpose. > =20 > -The arm and arm64 architectures directly map this to the arch_topology d= river > +The arm, arm64, and RISC-V architectures directly map this to the arch_t= opology driver My grep clearly missed this change, thanks. For the only part of the patch I understand: Reviewed-by: Conor Dooley Thanks, Conor. --Qu+vqTjLVyvhigH7 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHQEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY/yacQAKCRB4tDGHoIJi 0jMuAPUS3U8wKt0dDvUC5JFcU2VrD5RRUuYkkJESmDvd+oMvAPsE9NZjwV40Eqvv MRChuLnLfK6qyIngBouG73xf0TMeBQ== =v5xR -----END PGP SIGNATURE----- --Qu+vqTjLVyvhigH7-- --===============1929429015146575580== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============1929429015146575580==--