* [PATCH v2 0/3] Add RISC-V 32 NOMMU support
@ 2023-02-12 20:55 Jesse Taube
2023-02-12 20:55 ` [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division Jesse Taube
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Jesse Taube @ 2023-02-12 20:55 UTC (permalink / raw)
To: linux-riscv
Cc: linux-kernel, Jesse Taube, Yimin Gu, Waldemar Brodkorb, Albert Ou,
Palmer Dabbelt, Paul Walmsley
This patch-set aims to add NOMMU support to RV32.
Many people want to build simple emulators or HDL
models of RISC-V this patch makes it possible to
run linux on them.
Yimin Gu is the original author of this set.
Submitted here:
https://lists.buildroot.org/pipermail/buildroot/2022-November/656134.html
Though Jesse T rewrote the Dconf.
The new set:
https://lists.buildroot.org/pipermail/buildroot/2022-December/658258.html
---
V1->V2:
- Add Conor's clock patch for implicit div64
- Fix typo in commit title 3/3
- Fix typo in commit description 2/3
---
Conor Dooley (1):
clk: k210: remove an implicit 64-bit division
Jesse Taube (1):
riscv: configs: Add nommu defconfig for RV32
Yimin Gu (1):
riscv: Kconfig: Allow RV32 to build with no MMU
arch/riscv/Kconfig | 5 ++---
arch/riscv/configs/rv32_nommu_virt_defconfig | 16 ++++++++++++++++
drivers/clk/clk-k210.c | 2 +-
3 files changed, 19 insertions(+), 4 deletions(-)
create mode 100644 arch/riscv/configs/rv32_nommu_virt_defconfig
--
2.39.0
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division 2023-02-12 20:55 [PATCH v2 0/3] Add RISC-V 32 NOMMU support Jesse Taube @ 2023-02-12 20:55 ` Jesse Taube 2023-02-13 19:42 ` Conor Dooley 2023-02-12 20:55 ` [PATCH v2 2/3] riscv: Kconfig: Allow RV32 to build with no MMU Jesse Taube 2023-02-12 20:55 ` [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 Jesse Taube 2 siblings, 1 reply; 8+ messages in thread From: Jesse Taube @ 2023-02-12 20:55 UTC (permalink / raw) To: linux-riscv Cc: linux-kernel, Jesse Taube, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley, Conor Dooley, kernel test robot From: Conor Dooley <conor.dooley@microchip.com> The K210 clock driver depends on SOC_CANAAN, which is only selectable when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches have been sent for its enabling. The kernel test robot reported this implicit 64-bit division there. Replace the implicit division with an explicit one. Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/linux-riscv/202301201538.zNlqgE4L-lkp@intel.com/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> --- drivers/clk/clk-k210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c index 67a7cb3503c3..4eed667eddaf 100644 --- a/drivers/clk/clk-k210.c +++ b/drivers/clk/clk-k210.c @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw, f = FIELD_GET(K210_PLL_CLKF, reg) + 1; od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; - return (u64)parent_rate * f / (r * od); + return div_u64((u64)parent_rate * f, r * od); } static const struct clk_ops k210_pll_ops = { -- 2.39.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division 2023-02-12 20:55 ` [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division Jesse Taube @ 2023-02-13 19:42 ` Conor Dooley 0 siblings, 0 replies; 8+ messages in thread From: Conor Dooley @ 2023-02-13 19:42 UTC (permalink / raw) To: Jesse Taube Cc: linux-riscv, linux-kernel, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley, Conor Dooley, kernel test robot [-- Attachment #1.1: Type: text/plain, Size: 1475 bytes --] On Sun, Feb 12, 2023 at 03:55:04PM -0500, Jesse Taube wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The K210 clock driver depends on SOC_CANAAN, which is only selectable > when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches > have been sent for its enabling. The kernel test robot reported this > implicit 64-bit division there. > > Replace the implicit division with an explicit one. > > Reported-by: kernel test robot <lkp@intel.com> > Link: https://lore.kernel.org/linux-riscv/202301201538.zNlqgE4L-lkp@intel.com/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> btw, you'll need to run get_maintainer.pl on this patch so that the k210 and clock maintainers are CCed. It's also worth adding Damien Le Moal <damien.lemoal@wdc.com> > --- > drivers/clk/clk-k210.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c > index 67a7cb3503c3..4eed667eddaf 100644 > --- a/drivers/clk/clk-k210.c > +++ b/drivers/clk/clk-k210.c > @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw, > f = FIELD_GET(K210_PLL_CLKF, reg) + 1; > od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; > > - return (u64)parent_rate * f / (r * od); > + return div_u64((u64)parent_rate * f, r * od); > } > > static const struct clk_ops k210_pll_ops = { > -- > 2.39.0 > [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] riscv: Kconfig: Allow RV32 to build with no MMU 2023-02-12 20:55 [PATCH v2 0/3] Add RISC-V 32 NOMMU support Jesse Taube 2023-02-12 20:55 ` [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division Jesse Taube @ 2023-02-12 20:55 ` Jesse Taube 2023-02-12 20:55 ` [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 Jesse Taube 2 siblings, 0 replies; 8+ messages in thread From: Jesse Taube @ 2023-02-12 20:55 UTC (permalink / raw) To: linux-riscv Cc: linux-kernel, Jesse Taube, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley From: Yimin Gu <ustcymgu@gmail.com> Some RISC-V 32bit cores do not have an MMU, and the kernel should be able to build for them. This patch enables the RV32 to be built with no MMU support. Signed-off-by: Yimin Gu <ustcymgu@gmail.com> CC: Jesse Taube <Mr.Bossman075@gmail.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> --- arch/riscv/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 59d18881f35b..49759dbe6a8f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -163,8 +163,8 @@ config MMU config PAGE_OFFSET hex - default 0xC0000000 if 32BIT - default 0x80000000 if 64BIT && !MMU + default 0xC0000000 if 32BIT && MMU + default 0x80000000 if !MMU default 0xff60000000000000 if 64BIT config KASAN_SHADOW_OFFSET @@ -262,7 +262,6 @@ config ARCH_RV32I select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_LSHRDI3 select GENERIC_LIB_UCMPDI2 - select MMU config ARCH_RV64I bool "RV64I" -- 2.39.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 2023-02-12 20:55 [PATCH v2 0/3] Add RISC-V 32 NOMMU support Jesse Taube 2023-02-12 20:55 ` [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division Jesse Taube 2023-02-12 20:55 ` [PATCH v2 2/3] riscv: Kconfig: Allow RV32 to build with no MMU Jesse Taube @ 2023-02-12 20:55 ` Jesse Taube 2023-02-13 19:49 ` Conor Dooley 2 siblings, 1 reply; 8+ messages in thread From: Jesse Taube @ 2023-02-12 20:55 UTC (permalink / raw) To: linux-riscv Cc: linux-kernel, Jesse Taube, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley 32bit risc-v can be configured to run without MMU. This patch adds an example configuration for RV32 nommu virtual machine. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Cc: Yimin Gu <ustcymgu@gmail.com> --- arch/riscv/configs/rv32_nommu_virt_defconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 arch/riscv/configs/rv32_nommu_virt_defconfig diff --git a/arch/riscv/configs/rv32_nommu_virt_defconfig b/arch/riscv/configs/rv32_nommu_virt_defconfig new file mode 100644 index 000000000000..460907253a80 --- /dev/null +++ b/arch/riscv/configs/rv32_nommu_virt_defconfig @@ -0,0 +1,16 @@ +CONFIG_BLK_DEV_INITRD=y +# CONFIG_MMU is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_SOC_VIRT=y +CONFIG_NONPORTABLE=y +CONFIG_ARCH_RV32I=y +CONFIG_BINFMT_FLAT=y +CONFIG_SLOB=y +CONFIG_VIRTIO_BLK=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_EXT2_FS=y +CONFIG_PRINTK_TIME=y -- 2.39.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 2023-02-12 20:55 ` [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 Jesse Taube @ 2023-02-13 19:49 ` Conor Dooley 2023-02-13 21:44 ` Jesse Taube 0 siblings, 1 reply; 8+ messages in thread From: Conor Dooley @ 2023-02-13 19:49 UTC (permalink / raw) To: Jesse Taube Cc: linux-riscv, linux-kernel, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley [-- Attachment #1.1: Type: text/plain, Size: 1020 bytes --] Hey Jesse, On Sun, Feb 12, 2023 at 03:55:06PM -0500, Jesse Taube wrote: > 32bit risc-v can be configured to run without MMU. This patch adds > an example configuration for RV32 nommu virtual machine. There's a patch on the list (I think it came in after you sent v1) that pointed out that the rv32_defconfig in the tree is not actually used if you do `make ARCH=riscv rv32_defconfig`, but instead a make target is used. How would you feel about replacing this final patch with the below? That way rv32_nommu_virt_defconfig would always be kept in sync with the rv64 version. Cheers, Conor. diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 7123511d977c..785d438ae5fe 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -173,3 +173,7 @@ rv64_randconfig: PHONY += rv32_defconfig rv32_defconfig: $(Q)$(MAKE) -f $(srctree)/Makefile defconfig 32-bit.config + +PHONY += rv32_nommu_virt_defconfig +rv32_nommu_virt_defconfig: + $(Q)$(MAKE) -f $(srctree)/Makefile nommu_virt_defconfig 32-bit.config [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 2023-02-13 19:49 ` Conor Dooley @ 2023-02-13 21:44 ` Jesse Taube 2023-02-13 21:48 ` Conor Dooley 0 siblings, 1 reply; 8+ messages in thread From: Jesse Taube @ 2023-02-13 21:44 UTC (permalink / raw) To: Conor Dooley Cc: linux-riscv, linux-kernel, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley On 2/13/23 14:49, Conor Dooley wrote: > Hey Jesse, > > On Sun, Feb 12, 2023 at 03:55:06PM -0500, Jesse Taube wrote: >> 32bit risc-v can be configured to run without MMU. This patch adds >> an example configuration for RV32 nommu virtual machine. > > There's a patch on the list (I think it came in after you sent v1) that > pointed out that the rv32_defconfig in the tree is not actually used if > you do `make ARCH=riscv rv32_defconfig`, but instead a make target is > used. Oh that's interesting. Why is it still int the tree? How would you feel about replacing this final patch with the > below? That way rv32_nommu_virt_defconfig would always be kept in sync > with the rv64 version. Sounds good! The only gripe I have is the nommu_virt_defconfig is not very minimal, but that's not my problem. Thanks, Jesse Taube > > Cheers, > Conor. > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 7123511d977c..785d438ae5fe 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -173,3 +173,7 @@ rv64_randconfig: > PHONY += rv32_defconfig > rv32_defconfig: > $(Q)$(MAKE) -f $(srctree)/Makefile defconfig 32-bit.config > + > +PHONY += rv32_nommu_virt_defconfig > +rv32_nommu_virt_defconfig: > + $(Q)$(MAKE) -f $(srctree)/Makefile nommu_virt_defconfig 32-bit.config > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 2023-02-13 21:44 ` Jesse Taube @ 2023-02-13 21:48 ` Conor Dooley 0 siblings, 0 replies; 8+ messages in thread From: Conor Dooley @ 2023-02-13 21:48 UTC (permalink / raw) To: Jesse Taube Cc: linux-riscv, linux-kernel, Yimin Gu, Waldemar Brodkorb, Albert Ou, Palmer Dabbelt, Paul Walmsley [-- Attachment #1.1: Type: text/plain, Size: 1644 bytes --] On Mon, Feb 13, 2023 at 04:44:29PM -0500, Jesse Taube wrote: > > > On 2/13/23 14:49, Conor Dooley wrote: > > Hey Jesse, > > > > On Sun, Feb 12, 2023 at 03:55:06PM -0500, Jesse Taube wrote: > > > 32bit risc-v can be configured to run without MMU. This patch adds > > > an example configuration for RV32 nommu virtual machine. > > > > There's a patch on the list (I think it came in after you sent v1) that > > pointed out that the rv32_defconfig in the tree is not actually used if > > you do `make ARCH=riscv rv32_defconfig`, but instead a make target is > > used. > Oh that's interesting. Why is it still int the tree? See that's the thing - the patch was deleting the rv32_defconfig file: https://lore.kernel.org/linux-riscv/20230205133307.1058814-1-guoren@kernel.org/ > > How would you feel about replacing this final patch with the > > below? That way rv32_nommu_virt_defconfig would always be kept in sync > > with the rv64 version. > Sounds good! The only gripe I have is the nommu_virt_defconfig is not very > minimal, but that's not my problem. > > Thanks, > Jesse Taube > > > > Cheers, > > Conor. > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > index 7123511d977c..785d438ae5fe 100644 > > --- a/arch/riscv/Makefile > > +++ b/arch/riscv/Makefile > > @@ -173,3 +173,7 @@ rv64_randconfig: > > PHONY += rv32_defconfig > > rv32_defconfig: > > $(Q)$(MAKE) -f $(srctree)/Makefile defconfig 32-bit.config > > + > > +PHONY += rv32_nommu_virt_defconfig > > +rv32_nommu_virt_defconfig: > > + $(Q)$(MAKE) -f $(srctree)/Makefile nommu_virt_defconfig 32-bit.config > > [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-02-13 21:48 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-02-12 20:55 [PATCH v2 0/3] Add RISC-V 32 NOMMU support Jesse Taube 2023-02-12 20:55 ` [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division Jesse Taube 2023-02-13 19:42 ` Conor Dooley 2023-02-12 20:55 ` [PATCH v2 2/3] riscv: Kconfig: Allow RV32 to build with no MMU Jesse Taube 2023-02-12 20:55 ` [PATCH v2 3/3] riscv: configs: Add nommu defconfig for RV32 Jesse Taube 2023-02-13 19:49 ` Conor Dooley 2023-02-13 21:44 ` Jesse Taube 2023-02-13 21:48 ` Conor Dooley
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