Re: [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions

Heiko Stuebner
2022-10-13T13:47:27Z

Am Freitag, 7. Oktober 2022, 13:54:31 CEST schrieb Heiko Stübner:
> Am Donnerstag, 6. Oktober 2022, 09:08:14 CEST schrieb Jisheng Zhang:
> > make the riscv_cpufeature_patch_func() scan all ISA extensions rather
> > than limited feature macros.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>

[...]

> > @@ -127,7 +124,7 @@ asm volatile(ALTERNATIVE_2( \
> > "add a0, a0, %0\n\t" \
> > "2:\n\t" \
> > "bltu a0, %2, 3b\n\t" \
> > - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
> > + "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
>
> hmm, would it make sense to also at the same time extend the errata_id
> in the alternatives struct to unsigned long?
>
> Right now it's a unsigned int, and we're already at bit30 with the current extensions.
>
> Otherwise the idea is pretty neat of allowing easy handling for all extensions
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>

I think I might need to take that back ... with this change each
cpufeature is tightly coupled to real extension ids, but what about
cpufeatures that do not match directly to an extension?

I.e. ZICBOM + fast-unaligned-access [0] (coming from a dt-property)
or only viable with extension 1+2+3?

Heiko

[0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe&id=9be297f7ed349945cccc85f8df9d90e5ab68c1d9