From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>,
Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH 3/3] RISC-V: Ensure Zicbom has a valid block size
Date: Sun, 23 Oct 2022 20:38:55 +0100 [thread overview]
Message-ID: <Y1WYT97IQy3Q6BhF@spud> (raw)
In-Reply-To: <20221021105905.206385-4-ajones@ventanamicro.com>
On Fri, Oct 21, 2022 at 12:59:05PM +0200, Andrew Jones wrote:
> When a DT puts zicbom in the isa string, but does not provide a block
> size, ALT_CMO_OP() will attempt to do cache operations on address
> zero since the start address will be ANDed with zero. We can't simply
> BUG() in riscv_init_cbom_blocksize() when we fail to find a block
> size because the failure will happen before logging works, leaving
> users to scratch their heads as to why the boot hung. Instead, ensure
> Zicbom is disabled and output an error which will hopefully alert
> people that the DT needs to be fixed. While at it, add a check that
> the block size is a power-of-2 too.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kernel/cpufeature.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 220be7222129..a4430a77df53 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -9,6 +9,7 @@
> #include <linux/bitmap.h>
> #include <linux/ctype.h>
> #include <linux/libfdt.h>
> +#include <linux/log2.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <asm/alternative.h>
> @@ -70,6 +71,20 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
>
> static bool riscv_isa_extension_check(int id)
> {
> + switch (id) {
> + case RISCV_ISA_EXT_ZICBOM:
> + if (!riscv_cbom_block_size) {
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
Maybe I've missed something... Why not check if !IS_ENABLED() & return
false immediately rather than doing it inside the attribute checks?
I'll be compiled out of zicbom is enabled, so not like the non-error
patch will be penalised with an extra check.
> + pr_err("cbom-block-size not found, cannot use Zicbom\n");
> + return false;
> + } else if (!is_power_of_2(riscv_cbom_block_size)) {
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
> + pr_err("cbom-block-size is not a power-of-2, cannot use Zicbom\n");
> + return false;
> + }
> + return true;
> + }
> +
> return true;
> }
>
> --
> 2.37.3
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2022-10-23 19:39 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-21 10:59 [PATCH 0/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-21 10:59 ` [PATCH 1/3] RISC-V: Improve use of isa2hwcap[] Andrew Jones
2022-10-23 19:28 ` Conor Dooley
2022-10-24 6:48 ` Andrew Jones
2022-10-24 7:16 ` Conor Dooley
2022-10-21 10:59 ` [PATCH 2/3] RISC-V: Introduce riscv_isa_extension_check Andrew Jones
2022-10-23 19:32 ` Conor Dooley
2022-10-21 10:59 ` [PATCH 3/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-23 19:38 ` Conor Dooley [this message]
2022-10-24 7:09 ` Andrew Jones
2022-10-24 8:17 ` Conor Dooley
2022-10-24 8:35 ` Andrew Jones
2022-10-24 9:26 ` Conor Dooley
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