From: Conor Dooley <conor@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>, arnd@arndb.de
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Mayuresh Chitale <mchitale@ventanamicro.com>
Subject: Re: [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
Date: Mon, 24 Oct 2022 20:54:13 +0100 [thread overview]
Message-ID: <Y1btZRX/e+c+UDyv@spud> (raw)
In-Reply-To: <20221020075846.305576-3-apatel@ventanamicro.com>
On Thu, Oct 20, 2022 at 01:28:44PM +0530, Anup Patel wrote:
> Currently, the memremap() called with MEMREMAP_WB maps memory using
> the generic ioremap() function which breaks on system with Svpbmt
> because memory mapped using _PAGE_IOREMAP page attributes is treated
> as strongly-ordered non-cacheable IO memory.
>
> To address this, we implement RISC-V specific arch_memremap_wb()
> which maps memory using _PAGE_KERNEL page attributes resulting in
> write-back cacheable mapping on systems with Svpbmt.
>
> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Hey Arnd,
Does this look okay to you now?
Thanks,
Conor.
> ---
> arch/riscv/include/asm/io.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index 92080a227937..42497d487a17 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
>
> #include <asm-generic/io.h>
>
> +#ifdef CONFIG_MMU
> +#define arch_memremap_wb(addr, size) \
> + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL))
> +#endif
> +
> #endif /* _ASM_RISCV_IO_H */
> --
> 2.34.1
>
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next prev parent reply other threads:[~2022-10-24 19:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 7:58 [PATCH v5 0/4] Add PMEM support for RISC-V Anup Patel
2022-10-20 7:58 ` [PATCH v5 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
2022-10-21 6:48 ` Anup Patel
2022-10-20 7:58 ` [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Anup Patel
2022-10-24 19:54 ` Conor Dooley [this message]
2022-10-20 7:58 ` [PATCH v5 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
2022-10-24 19:52 ` Conor Dooley
2022-11-14 9:02 ` Anup Patel
2022-10-20 7:58 ` [PATCH v5 4/4] RISC-V: Enable PMEM drivers Anup Patel
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