Re: [PATCH v1 8/9] PCI: microchip: Partition inbound address translation

Conor Dooley
2022-11-16T17:01:41Z

On Wed, Nov 16, 2022 at 10:49:33AM -0600, Bjorn Helgaas wrote:
> On Wed, Nov 16, 2022 at 01:55:03PM +0000, daire.mcnamara@microchip.com wrote:
> > From: Daire McNamara <daire.mcnamara@microchip.com>
> >
> > On Microchip PolarFire SoC the PCIe rootport is behind a set of fabric
> > inter connect (fic) busses that encapsulate busses like ABP/AHP, AXI-S
> > and AXI-M. Depending on which fic(s) the rootport is wired through to
> > cpu space, the rootport driver needs to take account of the address
> > translation done by a parent (e.g. fabric) node before setting up its
> > own inbound address translation tables from attached devices.
>
> Hi Daire, minor nits:
>
> s/inter connect/interconnect/
> s/fic/FIC/ ? Sounds like an initialism similar to ABP, AHP, etc?

Daire, we've been living a lie. The TRM says "Fabric Interface
Controllers (FICs)" so I think we should switch the that wording.
Fits the acronym better too..