Re: [PATCH RFC v2 1/3] riscv: add support for hardware breakpoints/watchpoints

Sergey Matyukevich
2022-12-05T07:23:20Z

> > RISC-V backend for hw-breakpoint framework is built on top of SBI Debug
> > Trigger extension. Architecture specific hooks are implemented as kernel
> > wrappers around ecalls to SBI functions. This patch implements only a
> > minimal set of hooks required to support user-space debug via ptrace.
> >
> > Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 2a0ef738695e..ef41d60a5ed3 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -31,6 +31,9 @@ enum sbi_ext_id {
> > SBI_EXT_SRST = 0x53525354,
> > SBI_EXT_PMU = 0x504D55,
> >
> > + /* Experimental: Debug Trigger Extension */
> > + SBI_EXT_DBTR = 0x44425452,
> > +
> > /* Experimentals extensions must lie within this range */
> > SBI_EXT_EXPERIMENTAL_START = 0x08000000,
> > SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
>
> This is an RFC for something I know nothing about, so was just scrolling
> mindlessly... This caught my eye as odd - There's an explicit comment
> about the range for experimental stuff but you've not used it? I guess
> there must be some reason for that?

IIUC it is not so experimental. This SBI extension accompanies the debug
spec v1.0 (frozen but not yet ratified). So sooner or later is going
to become a part of SBI spec.

I am using EID suggested in the draft v4 for this extension
posted at lists.riscv.org tech-debug mailing list, see:
https://lists.riscv.org/g/tech-debug/topic/92375492

Regards,
Sergey