[PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

Jisheng Zhang
2022-11-27T13:35:17Z

Add Jisheng Zhang as Bouffalolab SoC maintainer.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 00ff4a2949b8..a6b04249853c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17729,6 +17729,15 @@ F: arch/riscv/
N: riscv
K: riscv

+RISC-V BOUFFALOLAB SOC SUPPORT
+M: Jisheng Zhang <jszhang@kernel.org>
+L: linux-riscv@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/riscv/bouffalolab.yaml
+F: Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
+F: arch/riscv/boot/dts/bouffalolab/
+F: drivers/tty/serial/bflb_uart.c
+
RISC-V MICROCHIP FPGA SUPPORT
M: Conor Dooley <conor.dooley@microchip.com>
M: Daire McNamara <daire.mcnamara@microchip.com>
--
2.38.1