From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE20CC43217 for ; Fri, 25 Nov 2022 23:44:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vqBqiV9X96JmLQdatrjylr2Etg6x4ZjWU4H9tXSj3xw=; b=nyo5cPOkXa+PDs bq8uKZ0T9eK2BLnn7iYyxydpKy0UnzB6gTnkKgTPn5d2GprlQ9gHYs586XwRitUHX7UOsH9sAeso0 bI8+OnGWnG3WAajaqQ5VXynoPAr0ayh3yLVS9CrAuWs3uXtGAEDe9xPgz14I8FES7N9xlgFwgkKWs rfXRYJ83yNYJZR/KQwV9MazPK5k7HSGKtxODLXeoO+xt8dIE7wGhDQ3OA2VAFqXrt5eeEb3TDAEBF aAOTjU5SgzDd8sAN/BbaFBGa60PaDShctTWvrm+sN6Rp/j23tpA5qKwl1G2CN0cuxPYEIdq7Nel1m GL7Adn5nxF8O20nbxdzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyiMf-002tto-28; Fri, 25 Nov 2022 23:44:13 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyiMc-002tsC-0B for linux-riscv@lists.infradead.org; Fri, 25 Nov 2022 23:44:11 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CEEE7B82C8B; Fri, 25 Nov 2022 23:44:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 867C4C433D6; Fri, 25 Nov 2022 23:44:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669419846; bh=dx4KFqZ6EVEnjfrcSXRUt1F3Np6H36TlPzTa24JlEx4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ZihZxuLZ6WTXu6nyondE9tQSnFousiW66KNNMR8suvn9ygAJqzp4ufvTJbcothExe HNvsrPXtQoF8xhWyAUrH0Edp7GK2zaEOxx9Q9/QQ1apLau8oYjnKffLdy6GjP14iGm OhhEVjfxEQsGErGbID1aIY6kVXE2XX5E2jMsu7IjMqJVvCn+NVn5fSHFAz6xs86dt5 d3GyQP8sxUXbXJC1n2daiv+oyaPeHzEfbjSRAsguD4PRzMn3Ewxc27qXDZTZ5WVM2i R879aTdgDi+/06ZO/xHjwB8Q9ACve5H/o7qayY45TX95q7My4yzXF+go9UIpBF+3Za K2Rjb3MbrsOTw== Date: Fri, 25 Nov 2022 23:44:01 +0000 From: Conor Dooley To: Anup Patel Cc: Anup Patel , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner , Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Jisheng Zhang Subject: Re: [PATCH v3 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Message-ID: References: <20221125112105.427045-1-apatel@ventanamicro.com> <20221125112105.427045-4-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221125_154410_359873_D749B574 X-CRM114-Status: GOOD ( 38.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Nov 25, 2022 at 01:13:04PM +0000, Conor Dooley wrote: > On Fri, Nov 25, 2022 at 04:51:05PM +0530, Anup Patel wrote: > > We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only > > when riscv,timer-cant-wake-up DT property is present in the RISC-V > > timer DT node. > > > > This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device > > based on RISC-V platform capabilities rather than having it set for > > all RISC-V platforms. > > I need to go do some testing on what setting the C3STOP flag does on > platforms other than PolarFire SoC. I'm not sure that we should be > enabling this flag *at all* until we know that it does not break on > other platforms too. I tried my fu540 & fu740 - both of those seem to exhibit broken timer behaviour with C3STOP set. Ethernet doesn't work upstream on the VisionFive, so I didn't go through the hassle of testing that - but I would imagine it is the same as the fu740. Whenever I get a VisionFive 2 I'll give that a try too. I did try the D1 (thanks for fielding my dumb questions Samuel) but I was not able to get the thing to boot if I disabled the sunxi timer :/ Ethernet would not come up in U-Boot, clearly I did something not right.. Obviously we need to fix things & get it backported etc, so taking a pragmatic approach: I think that it is better to merge this stuff even though it there's a pretty good chance I think that it'll break the SBI timer on a D1, since it is not intended that it will be used. It does make me worried about some of the other platforms though, like that Bouffalolabs SoC that Jisheng sent in a DT for. It's also using thead stuff so I wonder if it needs C3STOP too. I've added Jisheng to CC :) > > Signed-off-by: Anup Patel > > --- > > drivers/clocksource/timer-riscv.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > > index a0d66fabf073..0c8bdd168a45 100644 > > --- a/drivers/clocksource/timer-riscv.c > > +++ b/drivers/clocksource/timer-riscv.c > > @@ -28,6 +28,7 @@ > > #include > > > > static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); > > +static bool riscv_timer_cant_wake_cpu; > > > > static int riscv_clock_next_event(unsigned long delta, > > struct clock_event_device *ce) > > @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) > > > > ce->cpumask = cpumask_of(cpu); > > ce->irq = riscv_clock_event_irq; > > + if (riscv_timer_cant_wake_cpu) > > + ce->features |= CLOCK_EVT_FEAT_C3STOP; > > clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); > > > > enable_percpu_irq(riscv_clock_event_irq, > > @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) > > if (cpuid != smp_processor_id()) > > return 0; > > > > + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); > > + if (child) { > > + riscv_timer_cant_wake_cpu = of_property_read_bool(child, > > + "riscv,timer-cant-wake-cpu"); > > + of_node_put(child); > > + } > > + > > domain = NULL; > > child = of_get_compatible_child(n, "riscv,cpu-intc"); > > if (!child) { Anyway, the mechanics of the change here look good to me. The re-use of child is understandable but a little odd though, since riscv,timer /is not/ actually a child. That's relatively minor thing to change though. I'm still not happy about turning on C3STOP when we have not figured out why it's breaking timer behaviour, but I think that's the lessor of two evils. Somewhat reluctantly: Reviewed-by: Conor Dooley I'll try to spend some time looking into why it's broken. Thanks, Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv