From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FDADC4708A for ; Tue, 29 Nov 2022 14:37:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3voYoUk25Z2eCJtNSeVFt8eMiyP5rgJrfypLxqwX4c0=; b=lJzKCLs9FZsViz QOhzBaREb1bBEkLHZ7tOx1jVYGP8xKUla6wdhXd0EeFO7JFybuY4v7bLacONq/5Xqy35drWTWfRQS +okWbXDtmpwXBfUE7M0IbNiwJHrGF6/DL1zXX2pFJOmvvMu4kP3bHLbba2SYP70pi6DLnxFv22U77 /ugWlveps1mNeOUePnJhxZD7aDCuArCtxBX+Nu1Dou8pX9cklMcMvygWD6wlNRMmaqAQRtcMJwumS TPmBH1Jg63i7vXG2gIqW5bAB2KX54WEaF7HbNIGivg4I4/SG14IT7c7StDF9DPxzCJ1XvYqJk8/DK Myw6sdsHtKsBjlpqaMWQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01jF-009Jum-EI; Tue, 29 Nov 2022 14:36:57 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01jA-009JpG-2i for linux-riscv@lists.infradead.org; Tue, 29 Nov 2022 14:36:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669732612; x=1701268612; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=joBDR/6R/yQ5IZXkVvlgcx/puPOD9ZA3pVYvhslPmAU=; b=RUUjMStUqqSCba+RlEX7ekeTSIJP3fCJak7hQRAjzZg2vAjpdmRGVMp1 mvh3ofq6D6p+Bzhlo9hPn2xFa3CkX1lBsPeK/5AihjF8XP8ILlNpWH447 Tgp2XL7vQnNdtHpTbbDv/b88uGT/6DzCCldJVrN+GnoH3ZDqXjnxsmtYA AvwmwmmOBSWQaJ92/qXIDXCfU4MM7nz3nuwJBK0x5xl1M5Z5totNdI3HM r8JkFIEK3nmZ8Iwqo2N2XHcmagP8z5eSFieMxVWUIu1uBbk6rUmw+k25R 6hSL31pBZi3xt5CuUGt+SgxP10AQZUnNmytxUT5MXhuTb9wffGOmdjtl/ w==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="189175751" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:36:47 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:36:47 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:36:45 -0700 Date: Tue, 29 Nov 2022 14:36:26 +0000 From: Conor Dooley To: Anup Patel CC: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner , Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , , , Subject: Re: [PATCH v4 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Message-ID: References: <20221129140313.886192-1-apatel@ventanamicro.com> <20221129140313.886192-4-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221129140313.886192-4-apatel@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_063652_253824_D0923DEC X-CRM114-Status: GOOD ( 22.88 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Nov 29, 2022 at 07:33:13PM +0530, Anup Patel wrote: > We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only > when riscv,timer-cant-wake-up DT property is present in the RISC-V > timer DT node. > > This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device > based on RISC-V platform capabilities rather than having it set for > all RISC-V platforms. > > Signed-off-by: Anup Patel I thought I had left an R-b on this one? Reviewed-by: Conor Dooley Also, I think that we need to backport *something* that disables C3STOP which is why I had suggested keeping the revert in place. Patch 1 of this series only solves the timer issues but does not restore sleep states to their prior behaviour, right? Either this patch or the revert needs to go to stable IMO. Thanks, Conor. > --- > drivers/clocksource/timer-riscv.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index 969a552da8d2..0c8bdd168a45 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -28,6 +28,7 @@ > #include > > static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); > +static bool riscv_timer_cant_wake_cpu; > > static int riscv_clock_next_event(unsigned long delta, > struct clock_event_device *ce) > @@ -51,7 +52,7 @@ static int riscv_clock_next_event(unsigned long delta, > static unsigned int riscv_clock_event_irq; > static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { > .name = "riscv_timer_clockevent", > - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP, > + .features = CLOCK_EVT_FEAT_ONESHOT, > .rating = 100, > .set_next_event = riscv_clock_next_event, > }; > @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) > > ce->cpumask = cpumask_of(cpu); > ce->irq = riscv_clock_event_irq; > + if (riscv_timer_cant_wake_cpu) > + ce->features |= CLOCK_EVT_FEAT_C3STOP; > clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); > > enable_percpu_irq(riscv_clock_event_irq, > @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) > if (cpuid != smp_processor_id()) > return 0; > > + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); > + if (child) { > + riscv_timer_cant_wake_cpu = of_property_read_bool(child, > + "riscv,timer-cant-wake-cpu"); > + of_node_put(child); > + } > + > domain = NULL; > child = of_get_compatible_child(n, "riscv,cpu-intc"); > if (!child) { > -- > 2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv