Re: [PATCH v2 07/13] RISC-V: add auipc elements to parse_asm header

Conor Dooley
2022-11-29T23:36:28Z

On Mon, Nov 28, 2022 at 11:26:26AM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
> RISC-V: add auipc elements to parse_asm header

This header is no longer called parse_asm ;)

> We will want to use the opcode parsing outside kdb as well and need

Will we? Commit bikeshedding time, but mentioning the motivation would
be appreciated.

> at least the auipc element there.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
> arch/riscv/include/asm/insn.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index bfd306f85ec7..f10cb0fdfa96 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -118,6 +118,7 @@
> #define RVC_C2_RD_OPOFF 7
>
> /* parts of opcode for RVG*/
> +#define RVG_OPCODE_AUIPC 0x17
> #define RVG_OPCODE_BRANCH 0x63
> #define RVG_OPCODE_JALR 0x67
> #define RVG_OPCODE_JAL 0x6f
> @@ -149,6 +150,7 @@
> #define RVG_FUNCT12_EBREAK 0x1
> #define RVG_FUNCT12_SRET 0x102
>
> +#define RVG_MATCH_AUIPC (RVG_OPCODE_AUIPC)
> #define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
> #define RVG_MATCH_JAL (RVG_OPCODE_JAL)
> #define RVG_MATCH_BEQ (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
> @@ -167,6 +169,7 @@
> #define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
> #define RVC_MATCH_C_EBREAK (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
>
> +#define RVG_MASK_AUIPC RV_INSN_OPCODE_MASK
> #define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
> #define RVG_MASK_JAL (RV_INSN_OPCODE_MASK)
> #define RVC_MASK_C_JALR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
> @@ -203,6 +206,7 @@ __RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
> #else
> #define riscv_insn_is_c_jal(opcode) 0
> #endif
> +__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
> __RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
> __RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
> __RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)

This fixes the build error that's been lingering for a few patches, so
please re-order things so as not to break bisection :)

With the nits above fixed & assuming that this survives as its own
commit:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.