Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding

Guo Ren
2022-12-27T02:48:05Z

Good catch. But I hope c906/910 can directly use paddr here. It's
unnecessary to cause software translation & mmu translation here.

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index b0add983530a..30650a0c4481 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -24,13 +24,13 @@ void arch_sync_dma_for_device(phys_addr_t paddr,
size_t size,

switch (dir) {
case DMA_TO_DEVICE:
- ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
+ ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size);
break;
case DMA_FROM_DEVICE:
- ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
+ ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size);
break;
case DMA_BIDIRECTIONAL:
- ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+ ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size);
break;
default:
break;
@@ -47,7 +47,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
break;
case DMA_FROM_DEVICE:
case DMA_BIDIRECTIONAL:
- ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+ ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size);
break;
default:
break;
@@ -57,8 +57,9 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
void arch_dma_prep_coherent(struct page *page, size_t size)
{
void *flush_addr = page_address(page);
+ phys_addr_t paddr = PFN_PHYS(page_to_pfn(x));

- ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
+ ALT_CMO_OP(flush, flush_addr, paddr, size, riscv_cbom_block_size);
}

On Tue, Dec 27, 2022 at 10:03 AM Icenowy Zheng <uwu@icenowy.me> wrote:
>
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> The code is tested on a LiteX SoC with OpenC906 core, and it
> successfully boots to Systemd on a SD card connected to LiteSDCard.
>
> This change should be not noticable on C906, but on multi-core C910
> cluster it should fixes something. Unfortunately TH1520 seems to be not
> so ready to test mainline patches on.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> --
> 2.38.1
>

--
Best Regards
Guo Ren