* [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
@ 2022-12-16 6:21 ` panqinglin2020
2022-12-19 21:51 ` Conor Dooley
2022-12-16 6:21 ` [PATCH v11 2/3] riscv: mm: support Svnapot in hugetlb page panqinglin2020
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: panqinglin2020 @ 2022-12-16 6:21 UTC (permalink / raw)
To: palmer, linux-riscv; +Cc: jeff, xuyinan, conor, ajones, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Add one alternative to enable/disable svnapot support, enable this static
key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
option is set. It will influence the behavior of has_svnapot. All code
dependent on svnapot should make sure that has_svnapot return true firstly.
Modify PTE definition for Svnapot, and creates some functions in pgtable.h
to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
64KB napot size is supported in spec, so some macros has only 64KB version.
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e1a9fa47f012..25c230e3bf61 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -397,6 +397,25 @@ config RISCV_ISA_C
If you don't know what to do here, say Y.
+config RISCV_ISA_SVNAPOT
+ bool "SVNAPOT extension support"
+ depends on 64BIT && MMU
+ select RISCV_ALTERNATIVE
+ default y
+ help
+ Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
+ time and enable its usage.
+
+ The SVNAPOT extension is used to mark contiguous PTEs as a range
+ of contiguous virtual-to-physical translations for a naturally
+ aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
+ size. When HUGETLBFS is also selected this option unconditionally
+ allocates some memory for each NAPOT page size supported by the kernel.
+ When optimizing for low memory consumption and for platforms without
+ the SVNAPOT extension, it may be better to say N here.
+
+ If you don't know what to do here, say Y.
+
config RISCV_ISA_SVPBMT
bool "SVPBMT extension support"
depends on 64BIT && MMU
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 4180312d2a70..beadb1126ed9 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -22,9 +22,10 @@
#define ERRATA_THEAD_NUMBER 3
#endif
-#define CPUFEATURE_SVPBMT 0
-#define CPUFEATURE_ZICBOM 1
-#define CPUFEATURE_NUMBER 2
+#define CPUFEATURE_SVPBMT 0
+#define CPUFEATURE_ZICBOM 1
+#define CPUFEATURE_SVNAPOT 2
+#define CPUFEATURE_NUMBER 3
#ifdef __ASSEMBLY__
@@ -156,6 +157,14 @@ asm volatile(ALTERNATIVE( \
: "=r" (__ovl) : \
: "memory")
+#define ALT_SVNAPOT(_val) \
+asm(ALTERNATIVE( \
+ "li %0, 0", \
+ "li %0, 1", \
+ 0, CPUFEATURE_SVNAPOT, CONFIG_RISCV_ISA_SVNAPOT) \
+ : "=r" (_val) : \
+ : "memory")
+
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 86328e3acb02..a8f1a390b1a4 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -54,6 +54,7 @@ extern unsigned long elf_hwcap;
*/
enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
+ RISCV_ISA_EXT_SVNAPOT,
RISCV_ISA_EXT_SVPBMT,
RISCV_ISA_EXT_ZICBOM,
RISCV_ISA_EXT_ZIHINTPAUSE,
@@ -88,7 +89,6 @@ static __always_inline int riscv_isa_ext2key(int num)
{
switch (num) {
case RISCV_ISA_EXT_f:
- return RISCV_ISA_EXT_KEY_FPU;
case RISCV_ISA_EXT_d:
return RISCV_ISA_EXT_KEY_FPU;
case RISCV_ISA_EXT_ZIHINTPAUSE:
diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 9f432c1b5289..24a3dd265183 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -16,11 +16,6 @@
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE - 1))
-#ifdef CONFIG_64BIT
-#define HUGE_MAX_HSTATE 2
-#else
-#define HUGE_MAX_HSTATE 1
-#endif
#define HPAGE_SHIFT PMD_SHIFT
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 42a042c0e13e..7a5097202e15 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -78,6 +78,40 @@ typedef struct {
*/
#define _PAGE_PFN_MASK GENMASK(53, 10)
+/*
+ * [63] Svnapot definitions:
+ * 0 Svnapot disabled
+ * 1 Svnapot enabled
+ */
+#define _PAGE_NAPOT_SHIFT 63
+#define _PAGE_NAPOT BIT(_PAGE_NAPOT_SHIFT)
+/*
+ * Only 64KB (order 4) napot ptes supported.
+ */
+#define NAPOT_CONT_ORDER_BASE 4
+enum napot_cont_order {
+ NAPOT_CONT64KB_ORDER = NAPOT_CONT_ORDER_BASE,
+ NAPOT_ORDER_MAX,
+};
+
+#define for_each_napot_order(order) \
+ for (order = NAPOT_CONT_ORDER_BASE; order < NAPOT_ORDER_MAX; order++)
+#define for_each_napot_order_rev(order) \
+ for (order = NAPOT_ORDER_MAX - 1; \
+ order >= NAPOT_CONT_ORDER_BASE; order--)
+#define napot_cont_order(val) (__builtin_ctzl((val.pte >> _PAGE_PFN_SHIFT) << 1))
+
+#define napot_cont_shift(order) ((order) + PAGE_SHIFT)
+#define napot_cont_size(order) BIT(napot_cont_shift(order))
+#define napot_cont_mask(order) (~(napot_cont_size(order) - 1UL))
+#define napot_pte_num(order) BIT(order)
+
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+#define HUGE_MAX_HSTATE (2 + (NAPOT_ORDER_MAX - NAPOT_CONT_ORDER_BASE))
+#else
+#define HUGE_MAX_HSTATE 2
+#endif
+
/*
* [62:61] Svpbmt Memory Type definitions:
*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 2359f1f9bda9..07213236b976 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -6,10 +6,12 @@
#ifndef _ASM_RISCV_PGTABLE_H
#define _ASM_RISCV_PGTABLE_H
+#include <linux/jump_label.h>
#include <linux/mmzone.h>
#include <linux/sizes.h>
#include <asm/pgtable-bits.h>
+#include <asm/hwcap.h>
#ifndef CONFIG_MMU
#define KERNEL_LINK_ADDR PAGE_OFFSET
@@ -264,10 +266,49 @@ static inline pte_t pud_pte(pud_t pud)
return __pte(pud_val(pud));
}
+static __always_inline bool has_svnapot(void)
+{
+ unsigned int _val;
+
+ ALT_SVNAPOT(_val);
+
+ return _val;
+}
+
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+
+static inline unsigned long pte_napot(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_NAPOT;
+}
+
+static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
+{
+ int pos = order - 1 + _PAGE_PFN_SHIFT;
+ unsigned long napot_bit = BIT(pos);
+ unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT);
+
+ return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT);
+}
+
+#else
+
+static inline unsigned long pte_napot(pte_t pte)
+{
+ return 0;
+}
+
+#endif /* CONFIG_RISCV_ISA_SVNAPOT */
+
/* Yields the page frame number (PFN) of a page table entry */
static inline unsigned long pte_pfn(pte_t pte)
{
- return __page_val_to_pfn(pte_val(pte));
+ unsigned long res = __page_val_to_pfn(pte_val(pte));
+
+ if (has_svnapot() && pte_napot(pte))
+ res = res & (res - 1UL);
+
+ return res;
}
#define pte_page(x) pfn_to_page(pte_pfn(x))
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index bf9dd6764bad..88495f5fcafd 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -165,6 +165,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
+ __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 93e45560af30..60ebe2f22112 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -228,6 +228,7 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
+ SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
}
#undef SET_ISA_EXT_MAP
}
@@ -275,6 +276,17 @@ void __init riscv_fill_hwcap(void)
}
#ifdef CONFIG_RISCV_ALTERNATIVE
+static bool __init_or_module cpufeature_probe_svnapot(unsigned int stage)
+{
+ if (!IS_ENABLED(CONFIG_RISCV_ISA_SVNAPOT))
+ return false;
+
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ return false;
+
+ return riscv_isa_extension_available(NULL, SVNAPOT);
+}
+
static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
{
if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
@@ -312,6 +324,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
{
u32 cpu_req_feature = 0;
+ if (cpufeature_probe_svnapot(stage))
+ cpu_req_feature |= BIT(CPUFEATURE_SVNAPOT);
+
if (cpufeature_probe_svpbmt(stage))
cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
--
2.37.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot
2022-12-16 6:21 ` [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot panqinglin2020
@ 2022-12-19 21:51 ` Conor Dooley
2022-12-26 16:01 ` Andrew Jones
0 siblings, 1 reply; 15+ messages in thread
From: Conor Dooley @ 2022-12-19 21:51 UTC (permalink / raw)
To: panqinglin2020; +Cc: palmer, linux-riscv, jeff, xuyinan, ajones
[-- Attachment #1.1: Type: text/plain, Size: 10016 bytes --]
On Fri, Dec 16, 2022 at 02:21:07PM +0800, panqinglin2020@iscas.ac.cn wrote:
> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>
> Add one alternative to enable/disable svnapot support, enable this static
> key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
> option is set. It will influence the behavior of has_svnapot. All code
> dependent on svnapot should make sure that has_svnapot return true firstly.
>
> Modify PTE definition for Svnapot, and creates some functions in pgtable.h
> to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
> 64KB napot size is supported in spec, so some macros has only 64KB version.
>
> Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e1a9fa47f012..25c230e3bf61 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -397,6 +397,25 @@ config RISCV_ISA_C
>
> If you don't know what to do here, say Y.
>
> +config RISCV_ISA_SVNAPOT
> + bool "SVNAPOT extension support"
> + depends on 64BIT && MMU
> + select RISCV_ALTERNATIVE
> + default y
> + help
> + Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
> + time and enable its usage.
> +
> + The SVNAPOT extension is used to mark contiguous PTEs as a range
> + of contiguous virtual-to-physical translations for a naturally
> + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> + size. When HUGETLBFS is also selected this option unconditionally
> + allocates some memory for each NAPOT page size supported by the kernel.
> + When optimizing for low memory consumption and for platforms without
nit: Does this make more sense as "When optimising for low memory
consumption on platforms without the SVNAPOT extension"...?
Or does disabling Svnapot save memory on Svnapot capable systems too?
Thanks,
Conor.
> + the SVNAPOT extension, it may be better to say N here.
> +
> + If you don't know what to do here, say Y.
> +
> config RISCV_ISA_SVPBMT
> bool "SVPBMT extension support"
> depends on 64BIT && MMU
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..beadb1126ed9 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -22,9 +22,10 @@
> #define ERRATA_THEAD_NUMBER 3
> #endif
>
> -#define CPUFEATURE_SVPBMT 0
> -#define CPUFEATURE_ZICBOM 1
> -#define CPUFEATURE_NUMBER 2
> +#define CPUFEATURE_SVPBMT 0
> +#define CPUFEATURE_ZICBOM 1
> +#define CPUFEATURE_SVNAPOT 2
> +#define CPUFEATURE_NUMBER 3
>
> #ifdef __ASSEMBLY__
>
> @@ -156,6 +157,14 @@ asm volatile(ALTERNATIVE( \
> : "=r" (__ovl) : \
> : "memory")
>
> +#define ALT_SVNAPOT(_val) \
> +asm(ALTERNATIVE( \
> + "li %0, 0", \
> + "li %0, 1", \
> + 0, CPUFEATURE_SVNAPOT, CONFIG_RISCV_ISA_SVNAPOT) \
> + : "=r" (_val) : \
> + : "memory")
> +
> #endif /* __ASSEMBLY__ */
>
> #endif
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 86328e3acb02..a8f1a390b1a4 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -54,6 +54,7 @@ extern unsigned long elf_hwcap;
> */
> enum riscv_isa_ext_id {
> RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
> + RISCV_ISA_EXT_SVNAPOT,
> RISCV_ISA_EXT_SVPBMT,
> RISCV_ISA_EXT_ZICBOM,
> RISCV_ISA_EXT_ZIHINTPAUSE,
> @@ -88,7 +89,6 @@ static __always_inline int riscv_isa_ext2key(int num)
> {
> switch (num) {
> case RISCV_ISA_EXT_f:
> - return RISCV_ISA_EXT_KEY_FPU;
> case RISCV_ISA_EXT_d:
> return RISCV_ISA_EXT_KEY_FPU;
> case RISCV_ISA_EXT_ZIHINTPAUSE:
> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
> index 9f432c1b5289..24a3dd265183 100644
> --- a/arch/riscv/include/asm/page.h
> +++ b/arch/riscv/include/asm/page.h
> @@ -16,11 +16,6 @@
> #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
> #define PAGE_MASK (~(PAGE_SIZE - 1))
>
> -#ifdef CONFIG_64BIT
> -#define HUGE_MAX_HSTATE 2
> -#else
> -#define HUGE_MAX_HSTATE 1
> -#endif
> #define HPAGE_SHIFT PMD_SHIFT
> #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
> #define HPAGE_MASK (~(HPAGE_SIZE - 1))
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 42a042c0e13e..7a5097202e15 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -78,6 +78,40 @@ typedef struct {
> */
> #define _PAGE_PFN_MASK GENMASK(53, 10)
>
> +/*
> + * [63] Svnapot definitions:
> + * 0 Svnapot disabled
> + * 1 Svnapot enabled
> + */
> +#define _PAGE_NAPOT_SHIFT 63
> +#define _PAGE_NAPOT BIT(_PAGE_NAPOT_SHIFT)
> +/*
> + * Only 64KB (order 4) napot ptes supported.
> + */
> +#define NAPOT_CONT_ORDER_BASE 4
> +enum napot_cont_order {
> + NAPOT_CONT64KB_ORDER = NAPOT_CONT_ORDER_BASE,
> + NAPOT_ORDER_MAX,
> +};
> +
> +#define for_each_napot_order(order) \
> + for (order = NAPOT_CONT_ORDER_BASE; order < NAPOT_ORDER_MAX; order++)
> +#define for_each_napot_order_rev(order) \
> + for (order = NAPOT_ORDER_MAX - 1; \
> + order >= NAPOT_CONT_ORDER_BASE; order--)
> +#define napot_cont_order(val) (__builtin_ctzl((val.pte >> _PAGE_PFN_SHIFT) << 1))
> +
> +#define napot_cont_shift(order) ((order) + PAGE_SHIFT)
> +#define napot_cont_size(order) BIT(napot_cont_shift(order))
> +#define napot_cont_mask(order) (~(napot_cont_size(order) - 1UL))
> +#define napot_pte_num(order) BIT(order)
> +
> +#ifdef CONFIG_RISCV_ISA_SVNAPOT
> +#define HUGE_MAX_HSTATE (2 + (NAPOT_ORDER_MAX - NAPOT_CONT_ORDER_BASE))
> +#else
> +#define HUGE_MAX_HSTATE 2
> +#endif
> +
> /*
> * [62:61] Svpbmt Memory Type definitions:
> *
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 2359f1f9bda9..07213236b976 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -6,10 +6,12 @@
> #ifndef _ASM_RISCV_PGTABLE_H
> #define _ASM_RISCV_PGTABLE_H
>
> +#include <linux/jump_label.h>
> #include <linux/mmzone.h>
> #include <linux/sizes.h>
>
> #include <asm/pgtable-bits.h>
> +#include <asm/hwcap.h>
>
> #ifndef CONFIG_MMU
> #define KERNEL_LINK_ADDR PAGE_OFFSET
> @@ -264,10 +266,49 @@ static inline pte_t pud_pte(pud_t pud)
> return __pte(pud_val(pud));
> }
>
> +static __always_inline bool has_svnapot(void)
> +{
> + unsigned int _val;
> +
> + ALT_SVNAPOT(_val);
> +
> + return _val;
> +}
> +
> +#ifdef CONFIG_RISCV_ISA_SVNAPOT
> +
> +static inline unsigned long pte_napot(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_NAPOT;
> +}
> +
> +static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
> +{
> + int pos = order - 1 + _PAGE_PFN_SHIFT;
> + unsigned long napot_bit = BIT(pos);
> + unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT);
> +
> + return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT);
> +}
> +
> +#else
> +
> +static inline unsigned long pte_napot(pte_t pte)
> +{
> + return 0;
> +}
> +
> +#endif /* CONFIG_RISCV_ISA_SVNAPOT */
> +
> /* Yields the page frame number (PFN) of a page table entry */
> static inline unsigned long pte_pfn(pte_t pte)
> {
> - return __page_val_to_pfn(pte_val(pte));
> + unsigned long res = __page_val_to_pfn(pte_val(pte));
> +
> + if (has_svnapot() && pte_napot(pte))
> + res = res & (res - 1UL);
> +
> + return res;
> }
>
> #define pte_page(x) pfn_to_page(pte_pfn(x))
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index bf9dd6764bad..88495f5fcafd 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -165,6 +165,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 93e45560af30..60ebe2f22112 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -228,6 +228,7 @@ void __init riscv_fill_hwcap(void)
> SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
> SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
> SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> + SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
> }
> #undef SET_ISA_EXT_MAP
> }
> @@ -275,6 +276,17 @@ void __init riscv_fill_hwcap(void)
> }
>
> #ifdef CONFIG_RISCV_ALTERNATIVE
> +static bool __init_or_module cpufeature_probe_svnapot(unsigned int stage)
> +{
> + if (!IS_ENABLED(CONFIG_RISCV_ISA_SVNAPOT))
> + return false;
> +
> + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> + return false;
> +
> + return riscv_isa_extension_available(NULL, SVNAPOT);
> +}
> +
> static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> {
> if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
> @@ -312,6 +324,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
> {
> u32 cpu_req_feature = 0;
>
> + if (cpufeature_probe_svnapot(stage))
> + cpu_req_feature |= BIT(CPUFEATURE_SVNAPOT);
> +
> if (cpufeature_probe_svpbmt(stage))
> cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
>
> --
> 2.37.4
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot
2022-12-19 21:51 ` Conor Dooley
@ 2022-12-26 16:01 ` Andrew Jones
2022-12-26 18:40 ` Conor Dooley
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Jones @ 2022-12-26 16:01 UTC (permalink / raw)
To: Conor Dooley; +Cc: panqinglin2020, palmer, linux-riscv, jeff, xuyinan
On Mon, Dec 19, 2022 at 09:51:29PM +0000, Conor Dooley wrote:
> On Fri, Dec 16, 2022 at 02:21:07PM +0800, panqinglin2020@iscas.ac.cn wrote:
> > From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> >
> > Add one alternative to enable/disable svnapot support, enable this static
> > key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
> > option is set. It will influence the behavior of has_svnapot. All code
> > dependent on svnapot should make sure that has_svnapot return true firstly.
> >
> > Modify PTE definition for Svnapot, and creates some functions in pgtable.h
> > to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
> > 64KB napot size is supported in spec, so some macros has only 64KB version.
> >
> > Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index e1a9fa47f012..25c230e3bf61 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -397,6 +397,25 @@ config RISCV_ISA_C
> >
> > If you don't know what to do here, say Y.
> >
> > +config RISCV_ISA_SVNAPOT
> > + bool "SVNAPOT extension support"
> > + depends on 64BIT && MMU
> > + select RISCV_ALTERNATIVE
> > + default y
> > + help
> > + Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
> > + time and enable its usage.
> > +
> > + The SVNAPOT extension is used to mark contiguous PTEs as a range
> > + of contiguous virtual-to-physical translations for a naturally
> > + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> > + size. When HUGETLBFS is also selected this option unconditionally
> > + allocates some memory for each NAPOT page size supported by the kernel.
> > + When optimizing for low memory consumption and for platforms without
>
> nit: Does this make more sense as "When optimising for low memory
> consumption on platforms without the SVNAPOT extension"...?
> Or does disabling Svnapot save memory on Svnapot capable systems too?
Depends on how we define "save". Disabling RISCV_ISA_SVNAPOT on HUGETLBFS
enabled systems will reduce memory consumption whether the svnapot
extension is present or not. When the extension is present, the memory
consumed may serve a purpose, whereas, on systems without svnapot, the
memory consumed cannot serve a purpose.
Thanks,
drew
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot
2022-12-26 16:01 ` Andrew Jones
@ 2022-12-26 18:40 ` Conor Dooley
2022-12-26 19:19 ` Andrew Jones
0 siblings, 1 reply; 15+ messages in thread
From: Conor Dooley @ 2022-12-26 18:40 UTC (permalink / raw)
To: Andrew Jones; +Cc: panqinglin2020, palmer, linux-riscv, jeff, xuyinan
[-- Attachment #1.1: Type: text/plain, Size: 3005 bytes --]
On Mon, Dec 26, 2022 at 05:01:29PM +0100, Andrew Jones wrote:
> On Mon, Dec 19, 2022 at 09:51:29PM +0000, Conor Dooley wrote:
> > On Fri, Dec 16, 2022 at 02:21:07PM +0800, panqinglin2020@iscas.ac.cn wrote:
> > > From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> > >
> > > Add one alternative to enable/disable svnapot support, enable this static
> > > key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
> > > option is set. It will influence the behavior of has_svnapot. All code
> > > dependent on svnapot should make sure that has_svnapot return true firstly.
> > >
> > > Modify PTE definition for Svnapot, and creates some functions in pgtable.h
> > > to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
> > > 64KB napot size is supported in spec, so some macros has only 64KB version.
> > >
> > > Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > >
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index e1a9fa47f012..25c230e3bf61 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -397,6 +397,25 @@ config RISCV_ISA_C
> > >
> > > If you don't know what to do here, say Y.
> > >
> > > +config RISCV_ISA_SVNAPOT
> > > + bool "SVNAPOT extension support"
> > > + depends on 64BIT && MMU
> > > + select RISCV_ALTERNATIVE
> > > + default y
> > > + help
> > > + Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
> > > + time and enable its usage.
> > > +
> > > + The SVNAPOT extension is used to mark contiguous PTEs as a range
> > > + of contiguous virtual-to-physical translations for a naturally
> > > + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> > > + size. When HUGETLBFS is also selected this option unconditionally
> > > + allocates some memory for each NAPOT page size supported by the kernel.
> > > + When optimizing for low memory consumption and for platforms without
> >
> > nit: Does this make more sense as "When optimising for low memory
> > consumption on platforms without the SVNAPOT extension"...?
> > Or does disabling Svnapot save memory on Svnapot capable systems too?
>
> Depends on how we define "save". Disabling RISCV_ISA_SVNAPOT on HUGETLBFS
> enabled systems will reduce memory consumption whether the svnapot
> extension is present or not. When the extension is present, the memory
> consumed may serve a purpose, whereas, on systems without svnapot, the
> memory consumed cannot serve a purpose.
Right, thanks for the explanation. I'm sorry to be a bore here, but should
it be reworded then to "When optimising for low memory consumption on
platforms without SVNAPOT, or if HUGETLBFS is enabled, say N here"?
I don't really care either way to be perfectly honest, so as I said in
my other reply "don't bother resubmitting unless someone else asks for
meaningful changes" ;)
Conor.
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot
2022-12-26 18:40 ` Conor Dooley
@ 2022-12-26 19:19 ` Andrew Jones
2023-01-08 6:21 ` Qinglin Pan
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Jones @ 2022-12-26 19:19 UTC (permalink / raw)
To: Conor Dooley; +Cc: panqinglin2020, palmer, linux-riscv, jeff, xuyinan
On Mon, Dec 26, 2022 at 06:40:23PM +0000, Conor Dooley wrote:
> On Mon, Dec 26, 2022 at 05:01:29PM +0100, Andrew Jones wrote:
> > On Mon, Dec 19, 2022 at 09:51:29PM +0000, Conor Dooley wrote:
> > > On Fri, Dec 16, 2022 at 02:21:07PM +0800, panqinglin2020@iscas.ac.cn wrote:
> > > > From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> > > >
> > > > Add one alternative to enable/disable svnapot support, enable this static
> > > > key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
> > > > option is set. It will influence the behavior of has_svnapot. All code
> > > > dependent on svnapot should make sure that has_svnapot return true firstly.
> > > >
> > > > Modify PTE definition for Svnapot, and creates some functions in pgtable.h
> > > > to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
> > > > 64KB napot size is supported in spec, so some macros has only 64KB version.
> > > >
> > > > Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> > > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > > >
> > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > > index e1a9fa47f012..25c230e3bf61 100644
> > > > --- a/arch/riscv/Kconfig
> > > > +++ b/arch/riscv/Kconfig
> > > > @@ -397,6 +397,25 @@ config RISCV_ISA_C
> > > >
> > > > If you don't know what to do here, say Y.
> > > >
> > > > +config RISCV_ISA_SVNAPOT
> > > > + bool "SVNAPOT extension support"
> > > > + depends on 64BIT && MMU
> > > > + select RISCV_ALTERNATIVE
> > > > + default y
> > > > + help
> > > > + Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
> > > > + time and enable its usage.
> > > > +
> > > > + The SVNAPOT extension is used to mark contiguous PTEs as a range
> > > > + of contiguous virtual-to-physical translations for a naturally
> > > > + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> > > > + size. When HUGETLBFS is also selected this option unconditionally
> > > > + allocates some memory for each NAPOT page size supported by the kernel.
> > > > + When optimizing for low memory consumption and for platforms without
> > >
> > > nit: Does this make more sense as "When optimising for low memory
> > > consumption on platforms without the SVNAPOT extension"...?
> > > Or does disabling Svnapot save memory on Svnapot capable systems too?
> >
> > Depends on how we define "save". Disabling RISCV_ISA_SVNAPOT on HUGETLBFS
> > enabled systems will reduce memory consumption whether the svnapot
> > extension is present or not. When the extension is present, the memory
> > consumed may serve a purpose, whereas, on systems without svnapot, the
> > memory consumed cannot serve a purpose.
>
> Right, thanks for the explanation. I'm sorry to be a bore here, but should
> it be reworded then to "When optimising for low memory consumption on
> platforms without SVNAPOT, or if HUGETLBFS is enabled, say N here"?
I'd prefer we keep the instructions as simple as possible. Basically,
"Turn this off if you don't plan to use it and if you care about memory
consumption", which, IMHO, is how the text more or less already reads.
But...
>
> I don't really care either way to be perfectly honest, so as I said in
> my other reply "don't bother resubmitting unless someone else asks for
> meaningful changes" ;)
...I'm not too worried about it either, so I won't complain if Qinglin
respins with your suggestion.
Thanks,
drew
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot
2022-12-26 19:19 ` Andrew Jones
@ 2023-01-08 6:21 ` Qinglin Pan
0 siblings, 0 replies; 15+ messages in thread
From: Qinglin Pan @ 2023-01-08 6:21 UTC (permalink / raw)
To: Andrew Jones, Conor Dooley; +Cc: palmer, linux-riscv, jeff, xuyinan
Hi Andrew and Conor,
On 2022/12/27 03:19, Andrew Jones wrote:
> On Mon, Dec 26, 2022 at 06:40:23PM +0000, Conor Dooley wrote:
>> On Mon, Dec 26, 2022 at 05:01:29PM +0100, Andrew Jones wrote:
>>> On Mon, Dec 19, 2022 at 09:51:29PM +0000, Conor Dooley wrote:
>>>> On Fri, Dec 16, 2022 at 02:21:07PM +0800, panqinglin2020@iscas.ac.cn wrote:
>>>>> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>>>>>
>>>>> Add one alternative to enable/disable svnapot support, enable this static
>>>>> key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
>>>>> option is set. It will influence the behavior of has_svnapot. All code
>>>>> dependent on svnapot should make sure that has_svnapot return true firstly.
>>>>>
>>>>> Modify PTE definition for Svnapot, and creates some functions in pgtable.h
>>>>> to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
>>>>> 64KB napot size is supported in spec, so some macros has only 64KB version.
>>>>>
>>>>> Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>>>>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>>>>>
>>>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>>>> index e1a9fa47f012..25c230e3bf61 100644
>>>>> --- a/arch/riscv/Kconfig
>>>>> +++ b/arch/riscv/Kconfig
>>>>> @@ -397,6 +397,25 @@ config RISCV_ISA_C
>>>>>
>>>>> If you don't know what to do here, say Y.
>>>>>
>>>>> +config RISCV_ISA_SVNAPOT
>>>>> + bool "SVNAPOT extension support"
>>>>> + depends on 64BIT && MMU
>>>>> + select RISCV_ALTERNATIVE
>>>>> + default y
>>>>> + help
>>>>> + Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
>>>>> + time and enable its usage.
>>>>> +
>>>>> + The SVNAPOT extension is used to mark contiguous PTEs as a range
>>>>> + of contiguous virtual-to-physical translations for a naturally
>>>>> + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
>>>>> + size. When HUGETLBFS is also selected this option unconditionally
>>>>> + allocates some memory for each NAPOT page size supported by the kernel.
>>>>> + When optimizing for low memory consumption and for platforms without
>>>>
>>>> nit: Does this make more sense as "When optimising for low memory
>>>> consumption on platforms without the SVNAPOT extension"...?
>>>> Or does disabling Svnapot save memory on Svnapot capable systems too?
>>>
>>> Depends on how we define "save". Disabling RISCV_ISA_SVNAPOT on HUGETLBFS
>>> enabled systems will reduce memory consumption whether the svnapot
>>> extension is present or not. When the extension is present, the memory
>>> consumed may serve a purpose, whereas, on systems without svnapot, the
>>> memory consumed cannot serve a purpose.
>>
>> Right, thanks for the explanation. I'm sorry to be a bore here, but should
>> it be reworded then to "When optimising for low memory consumption on
>> platforms without SVNAPOT, or if HUGETLBFS is enabled, say N here"?
>
> I'd prefer we keep the instructions as simple as possible. Basically,
Sorry for slow reply.
I agree with Andrew, we should keep it as simple as possible. :)
So I will keep it unchanged unless any new suggestions about this
patchset is given.
Thanks,
Qinglin
> "Turn this off if you don't plan to use it and if you care about memory
> consumption", which, IMHO, is how the text more or less already reads.
> But...
>
>>
>> I don't really care either way to be perfectly honest, so as I said in
>> my other reply "don't bother resubmitting unless someone else asks for
>> meaningful changes" ;)
>
> ...I'm not too worried about it either, so I won't complain if Qinglin
> respins with your suggestion.
>
> Thanks,
> drew
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v11 2/3] riscv: mm: support Svnapot in hugetlb page
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
2022-12-16 6:21 ` [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot panqinglin2020
@ 2022-12-16 6:21 ` panqinglin2020
2022-12-16 6:21 ` [PATCH v11 3/3] riscv: mm: support Svnapot in huge vmap panqinglin2020
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: panqinglin2020 @ 2022-12-16 6:21 UTC (permalink / raw)
To: palmer, linux-riscv; +Cc: jeff, xuyinan, conor, ajones, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Svnapot can be used to support 64KB hugetlb page, so it can become a new
option when using hugetlbfs. Add a basic implementation of hugetlb page,
and support 64KB as a size in it by using Svnapot.
For test, boot kernel with command line contains "default_hugepagesz=64K
hugepagesz=64K hugepages=20" and run a simple test like this:
tools/testing/selftests/vm/map_hugetlb 1 16
And it should be passed.
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 25c230e3bf61..082bee28aabf 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,7 +44,7 @@ config RISCV
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
- select ARCH_WANT_GENERAL_HUGETLB
+ select ARCH_WANT_GENERAL_HUGETLB if !RISCV_ISA_SVNAPOT
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
diff --git a/arch/riscv/include/asm/hugetlb.h b/arch/riscv/include/asm/hugetlb.h
index ec19d6afc896..fe6f23006641 100644
--- a/arch/riscv/include/asm/hugetlb.h
+++ b/arch/riscv/include/asm/hugetlb.h
@@ -2,7 +2,6 @@
#ifndef _ASM_RISCV_HUGETLB_H
#define _ASM_RISCV_HUGETLB_H
-#include <asm-generic/hugetlb.h>
#include <asm/page.h>
static inline void arch_clear_hugepage_flags(struct page *page)
@@ -11,4 +10,37 @@ static inline void arch_clear_hugepage_flags(struct page *page)
}
#define arch_clear_hugepage_flags arch_clear_hugepage_flags
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+#define __HAVE_ARCH_HUGE_PTE_CLEAR
+void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, unsigned long sz);
+
+#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT
+void set_huge_pte_at(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep, pte_t pte);
+
+#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep);
+
+#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
+pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep);
+
+#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
+void huge_ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep);
+
+#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
+int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep,
+ pte_t pte, int dirty);
+
+pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags);
+#define arch_make_huge_pte arch_make_huge_pte
+
+#endif /*CONFIG_RISCV_ISA_SVNAPOT*/
+
+#include <asm-generic/hugetlb.h>
+
#endif /* _ASM_RISCV_HUGETLB_H */
diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c
index 932dadfdca54..31e83beaab42 100644
--- a/arch/riscv/mm/hugetlbpage.c
+++ b/arch/riscv/mm/hugetlbpage.c
@@ -2,6 +2,305 @@
#include <linux/hugetlb.h>
#include <linux/err.h>
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+ struct vm_area_struct *vma,
+ unsigned long addr,
+ unsigned long sz)
+{
+ unsigned long order;
+ pte_t *pte = NULL;
+ pgd_t *pgd;
+ p4d_t *p4d;
+ pud_t *pud;
+ pmd_t *pmd;
+
+ pgd = pgd_offset(mm, addr);
+ p4d = p4d_alloc(mm, pgd, addr);
+ if (!p4d)
+ return NULL;
+
+ pud = pud_alloc(mm, p4d, addr);
+ if (!pud)
+ return NULL;
+
+ if (sz == PUD_SIZE) {
+ pte = (pte_t *)pud;
+ goto out;
+ }
+
+ if (sz == PMD_SIZE) {
+ if (want_pmd_share(vma, addr) && pud_none(*pud))
+ pte = huge_pmd_share(mm, vma, addr, pud);
+ else
+ pte = (pte_t *)pmd_alloc(mm, pud, addr);
+ goto out;
+ }
+
+ pmd = pmd_alloc(mm, pud, addr);
+ if (!pmd)
+ return NULL;
+
+ for_each_napot_order(order) {
+ if (napot_cont_size(order) == sz) {
+ pte = pte_alloc_map(mm, pmd, addr & napot_cont_mask(order));
+ break;
+ }
+ }
+
+out:
+ WARN_ON_ONCE(pte && pte_present(*pte) && !pte_huge(*pte));
+ return pte;
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm,
+ unsigned long addr,
+ unsigned long sz)
+{
+ unsigned long order;
+ pte_t *pte = NULL;
+ pgd_t *pgd;
+ p4d_t *p4d;
+ pud_t *pud;
+ pmd_t *pmd;
+
+ pgd = pgd_offset(mm, addr);
+ if (!pgd_present(*pgd))
+ return NULL;
+
+ p4d = p4d_offset(pgd, addr);
+ if (!p4d_present(*p4d))
+ return NULL;
+
+ pud = pud_offset(p4d, addr);
+ if (sz == PUD_SIZE)
+ /* must be pud huge, non-present or none */
+ return (pte_t *)pud;
+
+ if (!pud_present(*pud))
+ return NULL;
+
+ pmd = pmd_offset(pud, addr);
+ if (sz == PMD_SIZE)
+ /* must be pmd huge, non-present or none */
+ return (pte_t *)pmd;
+
+ if (!pmd_present(*pmd))
+ return NULL;
+
+ for_each_napot_order(order) {
+ if (napot_cont_size(order) == sz) {
+ pte = pte_offset_kernel(pmd, addr & napot_cont_mask(order));
+ break;
+ }
+ }
+ return pte;
+}
+
+static pte_t get_clear_contig(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep,
+ unsigned long pte_num)
+{
+ pte_t orig_pte = ptep_get(ptep);
+ unsigned long i;
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++) {
+ pte_t pte = ptep_get_and_clear(mm, addr, ptep);
+
+ if (pte_dirty(pte))
+ orig_pte = pte_mkdirty(orig_pte);
+
+ if (pte_young(pte))
+ orig_pte = pte_mkyoung(orig_pte);
+ }
+
+ return orig_pte;
+}
+
+static pte_t get_clear_contig_flush(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep,
+ unsigned long pte_num)
+{
+ pte_t orig_pte = get_clear_contig(mm, addr, ptep, pte_num);
+ struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0);
+ bool valid = !pte_none(orig_pte);
+
+ if (valid)
+ flush_tlb_range(&vma, addr, addr + (PAGE_SIZE * pte_num));
+
+ return orig_pte;
+}
+
+pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags)
+{
+ unsigned long order;
+
+ for_each_napot_order(order) {
+ if (shift == napot_cont_shift(order)) {
+ entry = pte_mknapot(entry, order);
+ break;
+ }
+ }
+ if (order == NAPOT_ORDER_MAX)
+ entry = pte_mkhuge(entry);
+
+ return entry;
+}
+
+void set_huge_pte_at(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep,
+ pte_t pte)
+{
+ int i, pte_num;
+
+ if (!pte_napot(pte)) {
+ set_pte_at(mm, addr, ptep, pte);
+ return;
+ }
+
+ pte_num = napot_pte_num(napot_cont_order(pte));
+ for (i = 0; i < pte_num; i++, ptep++, addr += PAGE_SIZE)
+ set_pte_at(mm, addr, ptep, pte);
+}
+
+int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+ unsigned long addr,
+ pte_t *ptep,
+ pte_t pte,
+ int dirty)
+{
+ struct mm_struct *mm = vma->vm_mm;
+ unsigned long order;
+ pte_t orig_pte;
+ int i, pte_num;
+
+ if (!pte_napot(pte))
+ return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+
+ order = napot_cont_order(pte);
+ pte_num = napot_pte_num(order);
+ ptep = huge_pte_offset(mm, addr, napot_cont_size(order));
+ orig_pte = get_clear_contig_flush(mm, addr, ptep, pte_num);
+
+ if (pte_dirty(orig_pte))
+ pte = pte_mkdirty(pte);
+
+ if (pte_young(orig_pte))
+ pte = pte_mkyoung(pte);
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ set_pte_at(mm, addr, ptep, pte);
+
+ return true;
+}
+
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep)
+{
+ pte_t orig_pte = ptep_get(ptep);
+ int pte_num;
+
+ if (!pte_napot(orig_pte))
+ return ptep_get_and_clear(mm, addr, ptep);
+
+ pte_num = napot_pte_num(napot_cont_order(orig_pte));
+
+ return get_clear_contig(mm, addr, ptep, pte_num);
+}
+
+void huge_ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep)
+{
+ pte_t pte = ptep_get(ptep);
+ unsigned long order;
+ int i, pte_num;
+
+ if (!pte_napot(pte)) {
+ ptep_set_wrprotect(mm, addr, ptep);
+ return;
+ }
+
+ order = napot_cont_order(pte);
+ pte_num = napot_pte_num(order);
+ ptep = huge_pte_offset(mm, addr, napot_cont_size(order));
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ ptep_set_wrprotect(mm, addr, ptep);
+}
+
+pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
+ unsigned long addr,
+ pte_t *ptep)
+{
+ pte_t pte = ptep_get(ptep);
+ int pte_num;
+
+ if (!pte_napot(pte))
+ return ptep_clear_flush(vma, addr, ptep);
+
+ pte_num = napot_pte_num(napot_cont_order(pte));
+
+ return get_clear_contig_flush(vma->vm_mm, addr, ptep, pte_num);
+}
+
+void huge_pte_clear(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep,
+ unsigned long sz)
+{
+ pte_t pte = READ_ONCE(*ptep);
+ int i, pte_num;
+
+ if (!pte_napot(pte)) {
+ pte_clear(mm, addr, ptep);
+ return;
+ }
+
+ pte_num = napot_pte_num(napot_cont_order(pte));
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ pte_clear(mm, addr, ptep);
+}
+
+bool __init is_napot_size(unsigned long size)
+{
+ unsigned long order;
+
+ if (!has_svnapot())
+ return false;
+
+ for_each_napot_order(order) {
+ if (size == napot_cont_size(order))
+ return true;
+ }
+ return false;
+}
+
+static __init int napot_hugetlbpages_init(void)
+{
+ if (has_svnapot()) {
+ unsigned long order;
+
+ for_each_napot_order(order)
+ hugetlb_add_hstate(order);
+ }
+ return 0;
+}
+arch_initcall(napot_hugetlbpages_init);
+
+#else
+
+bool __init is_napot_size(unsigned long size)
+{
+ return false;
+}
+
+#endif /*CONFIG_RISCV_ISA_SVNAPOT*/
+
int pud_huge(pud_t pud)
{
return pud_leaf(pud);
@@ -18,6 +317,8 @@ bool __init arch_hugetlb_valid_size(unsigned long size)
return true;
else if (IS_ENABLED(CONFIG_64BIT) && size == PUD_SIZE)
return true;
+ else if (is_napot_size(size))
+ return true;
else
return false;
}
--
2.37.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v11 3/3] riscv: mm: support Svnapot in huge vmap
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
2022-12-16 6:21 ` [PATCH v11 1/3] riscv: mm: modify pte format for Svnapot panqinglin2020
2022-12-16 6:21 ` [PATCH v11 2/3] riscv: mm: support Svnapot in hugetlb page panqinglin2020
@ 2022-12-16 6:21 ` panqinglin2020
2022-12-19 21:48 ` [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime Conor Dooley
` (3 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: panqinglin2020 @ 2022-12-16 6:21 UTC (permalink / raw)
To: palmer, linux-riscv
Cc: jeff, xuyinan, conor, ajones, Qinglin Pan, Conor Dooley
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
As HAVE_ARCH_HUGE_VMAP and HAVE_ARCH_HUGE_VMALLOC is supported, we can
implement arch_vmap_pte_range_map_size and arch_vmap_pte_supported_shift
for Svnapot to support huge vmap about napot size.
It can be tested by huge vmap used in pci driver. Huge vmalloc with svnapot
can be tested by test_vmalloc with [1] applied, and probe this
module to run fix_size_alloc_test with use_huge true.
[1]https://lore.kernel.org/all/20221212055657.698420-1-panqinglin2020@iscas.ac.cn/
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/arch/riscv/include/asm/vmalloc.h b/arch/riscv/include/asm/vmalloc.h
index 48da5371f1e9..58d3e447f191 100644
--- a/arch/riscv/include/asm/vmalloc.h
+++ b/arch/riscv/include/asm/vmalloc.h
@@ -17,6 +17,65 @@ static inline bool arch_vmap_pmd_supported(pgprot_t prot)
return true;
}
-#endif
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
+#include <linux/pgtable.h>
+#define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size
+static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, unsigned long end,
+ u64 pfn, unsigned int max_page_shift)
+{
+ unsigned long map_size = PAGE_SIZE;
+ unsigned long size, order;
+
+ if (!has_svnapot())
+ return map_size;
+
+ for_each_napot_order_rev(order) {
+ if (napot_cont_shift(order) > max_page_shift)
+ continue;
+
+ size = napot_cont_size(order);
+ if (end - addr < size)
+ continue;
+
+ if (!IS_ALIGNED(addr, size))
+ continue;
+
+ if (!IS_ALIGNED(PFN_PHYS(pfn), size))
+ continue;
+
+ map_size = size;
+ break;
+ }
+
+ return map_size;
+}
+
+#define arch_vmap_pte_supported_shift arch_vmap_pte_supported_shift
+static inline int arch_vmap_pte_supported_shift(unsigned long size)
+{
+ int shift = PAGE_SHIFT;
+ unsigned long order;
+
+ if (!has_svnapot())
+ return shift;
+
+ WARN_ON_ONCE(size >= PMD_SIZE);
+
+ for_each_napot_order_rev(order) {
+ if (napot_cont_size(order) > size)
+ continue;
+
+ if (!IS_ALIGNED(size, napot_cont_size(order)))
+ continue;
+
+ shift = napot_cont_shift(order);
+ break;
+ }
+
+ return shift;
+}
+
+#endif /* CONFIG_RISCV_ISA_SVNAPOT */
+#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
#endif /* _ASM_RISCV_VMALLOC_H */
--
2.37.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
` (2 preceding siblings ...)
2022-12-16 6:21 ` [PATCH v11 3/3] riscv: mm: support Svnapot in huge vmap panqinglin2020
@ 2022-12-19 21:48 ` Conor Dooley
2023-01-14 4:54 ` Qinglin Pan
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Conor Dooley @ 2022-12-19 21:48 UTC (permalink / raw)
To: panqinglin2020; +Cc: palmer, linux-riscv, jeff, xuyinan, ajones
[-- Attachment #1.1: Type: text/plain, Size: 3682 bytes --]
On Fri, Dec 16, 2022 at 02:21:06PM +0800, panqinglin2020@iscas.ac.cn wrote:
> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>
> Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
> page. This patch set is for using Svnapot in hugetlb fs and huge vmap.
>
> This patchset adds a Kconfig item for using Svnapot in
> "Platform type"->"SVNAPOT extension support". Its default value is on,
> and people can set it off if they don't allow kernel to detect Svnapot
> hardware support and leverage it.
>
> Tested on:
> - qemu rv64 with "Svnapot support" off and svnapot=true.
> - qemu rv64 with "Svnapot support" on and svnapot=true.
> - qemu rv64 with "Svnapot support" off and svnapot=false.
> - qemu rv64 with "Svnapot support" on and svnapot=false.
>
>
> Changes in v2:
> - detect Svnapot hardware support at boot time.
> Changes in v3:
> - do linear mapping again if has_svnapot
> Changes in v4:
> - fix some errors/warns reported by checkpatch.pl, thanks @Conor
> Changes in v5:
> - modify code according to @Conor and @Heiko
> Changes in v6:
> - use static key insead of alternative errata
> Changes in v7:
> - add napot_cont_order for possible more napot order in the future
> - remove linear mapping related code from this patchset to another patch
> - refactor hugetlb code for svnapot according to thanks @Andrew @Conor
> - use tools/testing/selftests/vm/map_hugetlb as hugetlb testing program
> - support svnapot in huge vmap on newer for-next branch
> Changes in v8:
> - fix compilation errors in rv32_defconfig
> - insert some lines of whitespace according to @Conor's suggestion
> Changes in v9:
> - use alternative to avoid using static branches inside heavily used
> inline functions
> - change napot_cont_mask definition
> - post test_vmalloc modification about testing vmalloc_huge
> Changes in v10:
> - fix some nits caught by @Andrew
> - collect Reviewed-by/Acked-by
> - add memory leak warning in KConfig text
I got slightly confused between version as I was travelling - I saw 2
v10s so hopefully I have not missed anything. While "leak" is probably
not the right word to use here, I think the warning is a reasonable
compromise.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
I have one minor wording nit in patch 1/3, but don't bother resubmitting
unless someone else asks for meaningful changes.
Thanks,
Conor.
> - replace test_vmalloc patch link with the standard one
> Changes in v11:
> - add more detailed warning about HUGETLBFS and SVNAPOT in KConfig text
> - fix missing reverse-xmas tree
>
>
> Qinglin Pan (3):
> riscv: mm: modify pte format for Svnapot
> riscv: mm: support Svnapot in hugetlb page
> riscv: mm: support Svnapot in huge vmap
>
> arch/riscv/Kconfig | 21 +-
> arch/riscv/include/asm/errata_list.h | 15 +-
> arch/riscv/include/asm/hugetlb.h | 34 ++-
> arch/riscv/include/asm/hwcap.h | 2 +-
> arch/riscv/include/asm/page.h | 5 -
> arch/riscv/include/asm/pgtable-64.h | 34 +++
> arch/riscv/include/asm/pgtable.h | 43 +++-
> arch/riscv/include/asm/vmalloc.h | 61 +++++-
> arch/riscv/kernel/cpu.c | 1 +
> arch/riscv/kernel/cpufeature.c | 15 ++
> arch/riscv/mm/hugetlbpage.c | 301 +++++++++++++++++++++++++++
> 11 files changed, 519 insertions(+), 13 deletions(-)
>
> --
> 2.37.4
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
` (3 preceding siblings ...)
2022-12-19 21:48 ` [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime Conor Dooley
@ 2023-01-14 4:54 ` Qinglin Pan
2023-02-01 11:58 ` Qinglin Pan
2023-02-15 0:02 ` Palmer Dabbelt
6 siblings, 0 replies; 15+ messages in thread
From: Qinglin Pan @ 2023-01-14 4:54 UTC (permalink / raw)
To: palmer, linux-riscv; +Cc: jeff, xuyinan, conor, ajones
Hi Palmer,
a friendly ping?
Thanks,
Qinglin
On 2022/12/16 14:21, panqinglin2020@iscas.ac.cn wrote:
> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>
> Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
> page. This patch set is for using Svnapot in hugetlb fs and huge vmap.
>
> This patchset adds a Kconfig item for using Svnapot in
> "Platform type"->"SVNAPOT extension support". Its default value is on,
> and people can set it off if they don't allow kernel to detect Svnapot
> hardware support and leverage it.
>
> Tested on:
> - qemu rv64 with "Svnapot support" off and svnapot=true.
> - qemu rv64 with "Svnapot support" on and svnapot=true.
> - qemu rv64 with "Svnapot support" off and svnapot=false.
> - qemu rv64 with "Svnapot support" on and svnapot=false.
>
>
> Changes in v2:
> - detect Svnapot hardware support at boot time.
> Changes in v3:
> - do linear mapping again if has_svnapot
> Changes in v4:
> - fix some errors/warns reported by checkpatch.pl, thanks @Conor
> Changes in v5:
> - modify code according to @Conor and @Heiko
> Changes in v6:
> - use static key insead of alternative errata
> Changes in v7:
> - add napot_cont_order for possible more napot order in the future
> - remove linear mapping related code from this patchset to another patch
> - refactor hugetlb code for svnapot according to thanks @Andrew @Conor
> - use tools/testing/selftests/vm/map_hugetlb as hugetlb testing program
> - support svnapot in huge vmap on newer for-next branch
> Changes in v8:
> - fix compilation errors in rv32_defconfig
> - insert some lines of whitespace according to @Conor's suggestion
> Changes in v9:
> - use alternative to avoid using static branches inside heavily used
> inline functions
> - change napot_cont_mask definition
> - post test_vmalloc modification about testing vmalloc_huge
> Changes in v10:
> - fix some nits caught by @Andrew
> - collect Reviewed-by/Acked-by
> - add memory leak warning in KConfig text
> - replace test_vmalloc patch link with the standard one
> Changes in v11:
> - add more detailed warning about HUGETLBFS and SVNAPOT in KConfig text
> - fix missing reverse-xmas tree
>
>
> Qinglin Pan (3):
> riscv: mm: modify pte format for Svnapot
> riscv: mm: support Svnapot in hugetlb page
> riscv: mm: support Svnapot in huge vmap
>
> arch/riscv/Kconfig | 21 +-
> arch/riscv/include/asm/errata_list.h | 15 +-
> arch/riscv/include/asm/hugetlb.h | 34 ++-
> arch/riscv/include/asm/hwcap.h | 2 +-
> arch/riscv/include/asm/page.h | 5 -
> arch/riscv/include/asm/pgtable-64.h | 34 +++
> arch/riscv/include/asm/pgtable.h | 43 +++-
> arch/riscv/include/asm/vmalloc.h | 61 +++++-
> arch/riscv/kernel/cpu.c | 1 +
> arch/riscv/kernel/cpufeature.c | 15 ++
> arch/riscv/mm/hugetlbpage.c | 301 +++++++++++++++++++++++++++
> 11 files changed, 519 insertions(+), 13 deletions(-)
>
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
` (4 preceding siblings ...)
2023-01-14 4:54 ` Qinglin Pan
@ 2023-02-01 11:58 ` Qinglin Pan
2023-02-15 0:02 ` Palmer Dabbelt
6 siblings, 0 replies; 15+ messages in thread
From: Qinglin Pan @ 2023-02-01 11:58 UTC (permalink / raw)
To: palmer, linux-riscv; +Cc: jeff, xuyinan, conor, ajones
Hi Palmer,
Just a friendly ping :)
Is there anything else I need to do for this patchset?
Thanks,
Qinglin
On 2022/12/16 14:21, panqinglin2020@iscas.ac.cn wrote:
> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>
> Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
> page. This patch set is for using Svnapot in hugetlb fs and huge vmap.
>
> This patchset adds a Kconfig item for using Svnapot in
> "Platform type"->"SVNAPOT extension support". Its default value is on,
> and people can set it off if they don't allow kernel to detect Svnapot
> hardware support and leverage it.
>
> Tested on:
> - qemu rv64 with "Svnapot support" off and svnapot=true.
> - qemu rv64 with "Svnapot support" on and svnapot=true.
> - qemu rv64 with "Svnapot support" off and svnapot=false.
> - qemu rv64 with "Svnapot support" on and svnapot=false.
>
>
> Changes in v2:
> - detect Svnapot hardware support at boot time.
> Changes in v3:
> - do linear mapping again if has_svnapot
> Changes in v4:
> - fix some errors/warns reported by checkpatch.pl, thanks @Conor
> Changes in v5:
> - modify code according to @Conor and @Heiko
> Changes in v6:
> - use static key insead of alternative errata
> Changes in v7:
> - add napot_cont_order for possible more napot order in the future
> - remove linear mapping related code from this patchset to another patch
> - refactor hugetlb code for svnapot according to thanks @Andrew @Conor
> - use tools/testing/selftests/vm/map_hugetlb as hugetlb testing program
> - support svnapot in huge vmap on newer for-next branch
> Changes in v8:
> - fix compilation errors in rv32_defconfig
> - insert some lines of whitespace according to @Conor's suggestion
> Changes in v9:
> - use alternative to avoid using static branches inside heavily used
> inline functions
> - change napot_cont_mask definition
> - post test_vmalloc modification about testing vmalloc_huge
> Changes in v10:
> - fix some nits caught by @Andrew
> - collect Reviewed-by/Acked-by
> - add memory leak warning in KConfig text
> - replace test_vmalloc patch link with the standard one
> Changes in v11:
> - add more detailed warning about HUGETLBFS and SVNAPOT in KConfig text
> - fix missing reverse-xmas tree
>
>
> Qinglin Pan (3):
> riscv: mm: modify pte format for Svnapot
> riscv: mm: support Svnapot in hugetlb page
> riscv: mm: support Svnapot in huge vmap
>
> arch/riscv/Kconfig | 21 +-
> arch/riscv/include/asm/errata_list.h | 15 +-
> arch/riscv/include/asm/hugetlb.h | 34 ++-
> arch/riscv/include/asm/hwcap.h | 2 +-
> arch/riscv/include/asm/page.h | 5 -
> arch/riscv/include/asm/pgtable-64.h | 34 +++
> arch/riscv/include/asm/pgtable.h | 43 +++-
> arch/riscv/include/asm/vmalloc.h | 61 +++++-
> arch/riscv/kernel/cpu.c | 1 +
> arch/riscv/kernel/cpufeature.c | 15 ++
> arch/riscv/mm/hugetlbpage.c | 301 +++++++++++++++++++++++++++
> 11 files changed, 519 insertions(+), 13 deletions(-)
>
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime
2022-12-16 6:21 [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
` (5 preceding siblings ...)
2023-02-01 11:58 ` Qinglin Pan
@ 2023-02-15 0:02 ` Palmer Dabbelt
2023-02-15 2:47 ` Qinglin Pan
6 siblings, 1 reply; 15+ messages in thread
From: Palmer Dabbelt @ 2023-02-15 0:02 UTC (permalink / raw)
To: panqinglin2020
Cc: linux-riscv, jeff, xuyinan, Conor Dooley, ajones, panqinglin2020
On Thu, 15 Dec 2022 22:21:06 PST (-0800), panqinglin2020@iscas.ac.cn wrote:
> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>
> Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
> page. This patch set is for using Svnapot in hugetlb fs and huge vmap.
>
> This patchset adds a Kconfig item for using Svnapot in
> "Platform type"->"SVNAPOT extension support". Its default value is on,
> and people can set it off if they don't allow kernel to detect Svnapot
> hardware support and leverage it.
>
> Tested on:
> - qemu rv64 with "Svnapot support" off and svnapot=true.
> - qemu rv64 with "Svnapot support" on and svnapot=true.
> - qemu rv64 with "Svnapot support" off and svnapot=false.
> - qemu rv64 with "Svnapot support" on and svnapot=false.
>
>
> Changes in v2:
> - detect Svnapot hardware support at boot time.
> Changes in v3:
> - do linear mapping again if has_svnapot
> Changes in v4:
> - fix some errors/warns reported by checkpatch.pl, thanks @Conor
> Changes in v5:
> - modify code according to @Conor and @Heiko
> Changes in v6:
> - use static key insead of alternative errata
> Changes in v7:
> - add napot_cont_order for possible more napot order in the future
> - remove linear mapping related code from this patchset to another patch
> - refactor hugetlb code for svnapot according to thanks @Andrew @Conor
> - use tools/testing/selftests/vm/map_hugetlb as hugetlb testing program
> - support svnapot in huge vmap on newer for-next branch
> Changes in v8:
> - fix compilation errors in rv32_defconfig
> - insert some lines of whitespace according to @Conor's suggestion
> Changes in v9:
> - use alternative to avoid using static branches inside heavily used
> inline functions
> - change napot_cont_mask definition
> - post test_vmalloc modification about testing vmalloc_huge
> Changes in v10:
> - fix some nits caught by @Andrew
> - collect Reviewed-by/Acked-by
> - add memory leak warning in KConfig text
> - replace test_vmalloc patch link with the standard one
> Changes in v11:
> - add more detailed warning about HUGETLBFS and SVNAPOT in KConfig text
> - fix missing reverse-xmas tree
>
>
> Qinglin Pan (3):
> riscv: mm: modify pte format for Svnapot
> riscv: mm: support Svnapot in hugetlb page
> riscv: mm: support Svnapot in huge vmap
>
> arch/riscv/Kconfig | 21 +-
> arch/riscv/include/asm/errata_list.h | 15 +-
> arch/riscv/include/asm/hugetlb.h | 34 ++-
> arch/riscv/include/asm/hwcap.h | 2 +-
> arch/riscv/include/asm/page.h | 5 -
> arch/riscv/include/asm/pgtable-64.h | 34 +++
> arch/riscv/include/asm/pgtable.h | 43 +++-
> arch/riscv/include/asm/vmalloc.h | 61 +++++-
> arch/riscv/kernel/cpu.c | 1 +
> arch/riscv/kernel/cpufeature.c | 15 ++
> arch/riscv/mm/hugetlbpage.c | 301 +++++++++++++++++++++++++++
> 11 files changed, 519 insertions(+), 13 deletions(-)
This is triggering some build failures. I sent along a fix before
realizing they're actually coming from this patch set:
https://lore.kernel.org/all/20230214201358.10647-1-palmer@rivosinc.com/
. If it's OK I'll just squash that in here, so I can avoid a broken
build.
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime
2023-02-15 0:02 ` Palmer Dabbelt
@ 2023-02-15 2:47 ` Qinglin Pan
2023-02-16 22:04 ` Conor Dooley
0 siblings, 1 reply; 15+ messages in thread
From: Qinglin Pan @ 2023-02-15 2:47 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, jeff, xuyinan, Conor Dooley, ajones
Hi Palmer,
On 2/15/23 8:02 AM, Palmer Dabbelt wrote:
> On Thu, 15 Dec 2022 22:21:06 PST (-0800), panqinglin2020@iscas.ac.cn wrote:
>> From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
>>
>> Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
>> page. This patch set is for using Svnapot in hugetlb fs and huge vmap.
>>
>> This patchset adds a Kconfig item for using Svnapot in
>> "Platform type"->"SVNAPOT extension support". Its default value is on,
>> and people can set it off if they don't allow kernel to detect Svnapot
>> hardware support and leverage it.
>>
>> Tested on:
>> - qemu rv64 with "Svnapot support" off and svnapot=true.
>> - qemu rv64 with "Svnapot support" on and svnapot=true.
>> - qemu rv64 with "Svnapot support" off and svnapot=false.
>> - qemu rv64 with "Svnapot support" on and svnapot=false.
>>
>>
>> Changes in v2:
>> - detect Svnapot hardware support at boot time.
>> Changes in v3:
>> - do linear mapping again if has_svnapot
>> Changes in v4:
>> - fix some errors/warns reported by checkpatch.pl, thanks @Conor
>> Changes in v5:
>> - modify code according to @Conor and @Heiko
>> Changes in v6:
>> - use static key insead of alternative errata
>> Changes in v7:
>> - add napot_cont_order for possible more napot order in the future
>> - remove linear mapping related code from this patchset to another
>> patch
>> - refactor hugetlb code for svnapot according to thanks @Andrew @Conor
>> - use tools/testing/selftests/vm/map_hugetlb as hugetlb testing program
>> - support svnapot in huge vmap on newer for-next branch
>> Changes in v8:
>> - fix compilation errors in rv32_defconfig
>> - insert some lines of whitespace according to @Conor's suggestion
>> Changes in v9:
>> - use alternative to avoid using static branches inside heavily used
>> inline functions
>> - change napot_cont_mask definition
>> - post test_vmalloc modification about testing vmalloc_huge
>> Changes in v10:
>> - fix some nits caught by @Andrew
>> - collect Reviewed-by/Acked-by
>> - add memory leak warning in KConfig text
>> - replace test_vmalloc patch link with the standard one
>> Changes in v11:
>> - add more detailed warning about HUGETLBFS and SVNAPOT in KConfig text
>> - fix missing reverse-xmas tree
>>
>>
>> Qinglin Pan (3):
>> riscv: mm: modify pte format for Svnapot
>> riscv: mm: support Svnapot in hugetlb page
>> riscv: mm: support Svnapot in huge vmap
>>
>> arch/riscv/Kconfig | 21 +-
>> arch/riscv/include/asm/errata_list.h | 15 +-
>> arch/riscv/include/asm/hugetlb.h | 34 ++-
>> arch/riscv/include/asm/hwcap.h | 2 +-
>> arch/riscv/include/asm/page.h | 5 -
>> arch/riscv/include/asm/pgtable-64.h | 34 +++
>> arch/riscv/include/asm/pgtable.h | 43 +++-
>> arch/riscv/include/asm/vmalloc.h | 61 +++++-
>> arch/riscv/kernel/cpu.c | 1 +
>> arch/riscv/kernel/cpufeature.c | 15 ++
>> arch/riscv/mm/hugetlbpage.c | 301 +++++++++++++++++++++++++++
>> 11 files changed, 519 insertions(+), 13 deletions(-)
>
> This is triggering some build failures. I sent along a fix before
> realizing they're actually coming from this patch set:
> https://lore.kernel.org/all/20230214201358.10647-1-palmer@rivosinc.com/
> . If it's OK I'll just squash that in here, so I can avoid a broken build.
There is a newer v13(in [1]) based on new ISA extension API. But it
still have conchuod/build_rv64_gcc_allmodconfig check failed in it[2].
I have no idea whether it is caused by my patchset since the output
seems not related to my code.. Please let me know if there is anything I
need to modify.
[1]:
https://lore.kernel.org/linux-riscv/20230209131647.17245-1-panqinglin00@gmail.com/
[2]:
https://patchwork.kernel.org/project/linux-riscv/patch/20230209131647.17245-4-panqinglin00@gmail.com/
[3]: https://gist.github.com/conor-pwbot/0a1850594abdf3aebe4b3026a52a682d
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11 0/3] riscv, mm: detect svnapot cpu support at runtime
2023-02-15 2:47 ` Qinglin Pan
@ 2023-02-16 22:04 ` Conor Dooley
0 siblings, 0 replies; 15+ messages in thread
From: Conor Dooley @ 2023-02-16 22:04 UTC (permalink / raw)
To: Qinglin Pan; +Cc: Palmer Dabbelt, linux-riscv, jeff, xuyinan, ajones
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On Wed, Feb 15, 2023 at 10:47:49AM +0800, Qinglin Pan wrote:
> On 2/15/23 8:02 AM, Palmer Dabbelt wrote:
> > On Thu, 15 Dec 2022 22:21:06 PST (-0800), panqinglin2020@iscas.ac.cn wrote:
> > This is triggering some build failures. I sent along a fix before
> > realizing they're actually coming from this patch set:
> > https://lore.kernel.org/all/20230214201358.10647-1-palmer@rivosinc.com/
> > . If it's OK I'll just squash that in here, so I can avoid a broken
> > build.
>
> There is a newer v13(in [1]) based on new ISA extension API. But it still
> have conchuod/build_rv64_gcc_allmodconfig check failed in it[2].
> I have no idea whether it is caused by my patchset since the output seems
> not related to my code.. Please let me know if there is anything I
> need to modify.
Yah, looking at that it is actually just noise. For some reason the
before-the-patch build the scatterlist warnings got merged with other
warnings.
If you look at the "raw" version of the gist it's pretty easy to see:
https://gist.githubusercontent.com/conor-pwbot/0a1850594abdf3aebe4b3026a52a682d/raw/a5ed91502e27795c57c573824a66aff7f68f4323/stderr
I dunno what caused that, I'll have to take a look.
You can consider that one to be noise, sorry!
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^ permalink raw reply [flat|nested] 15+ messages in thread