Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding

Heiko Stuebner
2022-12-27T10:31:36Z

Am Dienstag, 27. Dezember 2022, 03:02:57 CET schrieb Icenowy Zheng:
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> The code is tested on a LiteX SoC with OpenC906 core, and it
> successfully boots to Systemd on a SD card connected to LiteSDCard.
>
> This change should be not noticable on C906, but on multi-core C910
> cluster it should fixes something. Unfortunately TH1520 seems to be not
> so ready to test mainline patches on.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"

the original encoding came from a chinese document from one of the
t-head repos which only containted the original instruction as
"dcache.cva" [0] ... so I guess some part was lost in translation :-)

It's really great to see that the documentation improved a lot with
that new repo with instruction encodings you mention in patch2.

Using that new repo you mention, the change looks correct
0x4 -> 0x5 for the instruction selection, so

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Though I'm on xmas vaction right now so can't test it on a board.

Heiko

[0] https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
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