[PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding

[PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding

[Icenowy Zheng]

The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
---
Included when resending:
- Sergey's Tested-by tag.

 arch/riscv/include/asm/errata_list.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 4180312d2a70..605800bd390e 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE(						\
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
  * dcache.cva rs1 (clean, virtual address)
- *   0000001    00100      rs1       000      00000  0001011
+ *   0000001    00101      rs1       000      00000  0001011
  *
  * dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE(						\
  *   0000000    11001     00000      000      00000  0001011
  */
 #define THEAD_inval_A0	".long 0x0265000b"
-#define THEAD_clean_A0	".long 0x0245000b"
+#define THEAD_clean_A0	".long 0x0255000b"
 #define THEAD_flush_A0	".long 0x0275000b"
 #define THEAD_SYNC_S	".long 0x0190000b"
 
-- 
2.38.1


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[PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.

[Icenowy Zheng]

T-Head now maintains some specification for their extended instructions
at [1], in which all instructions are prefixed "th.".

Follow this practice in the kernel comments.

[1] https://github.com/T-head-Semi/thead-extension-spec

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
 arch/riscv/include/asm/errata_list.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 605800bd390e..46adc1c9428f 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -92,25 +92,25 @@ asm volatile(ALTERNATIVE(						\
 #endif
 
 /*
- * dcache.ipa rs1 (invalidate, physical address)
+ * th.dcache.ipa rs1 (invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01010      rs1       000      00000  0001011
- * dache.iva rs1 (invalida, virtual address)
+ * th.dcache.iva rs1 (invalida, virtual address)
  *   0000001    00110      rs1       000      00000  0001011
  *
- * dcache.cpa rs1 (clean, physical address)
+ * th.dcache.cpa rs1 (clean, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
- * dcache.cva rs1 (clean, virtual address)
+ * th.dcache.cva rs1 (clean, virtual address)
  *   0000001    00101      rs1       000      00000  0001011
  *
- * dcache.cipa rs1 (clean then invalidate, physical address)
+ * th.dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01011      rs1       000      00000  0001011
- * dcache.civa rs1 (... virtual address)
+ * th.dcache.civa rs1 (... virtual address)
  *   0000001    00111      rs1       000      00000  0001011
  *
- * sync.s (make sure all cache operations finished)
+ * th.sync.s (make sure all cache operations finished)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000000    11001     00000      000      00000  0001011
  */
-- 
2.38.1


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Re: [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.

[Heiko Stübner]

Am Dienstag, 3. Januar 2023, 07:26:10 CET schrieb Icenowy Zheng:
> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
> 
> Follow this practice in the kernel comments.
> 
> [1] https://github.com/T-head-Semi/thead-extension-spec
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




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Re: [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.

[Conor Dooley]

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> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
> 
> Follow this practice in the kernel comments.
> 
> [1] https://github.com/T-head-Semi/thead-extension-spec
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Hey Icenowy,
This (yet again) appears to not have made it to the list.
It's not on patchwork, nor lore:
https://lore.kernel.org/linux-riscv/2668919.mvXUDI8C0e@diego/T/#t
https://lore.kernel.org/all/2668919.mvXUDI8C0e@diego/T/#t

Since you CCed lkml & not just linux-riscv, but it is not showing idk
what's wrong..
Your reply to me the other day came through:
https://lore.kernel.org/all/dda144a8397a175f3ce092485f08896c9a66d232.camel@icenowy.me/

Thanks,
Conor.


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Re: [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th.

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1138 bytes --]

On Tue, Jan 03, 2023 at 10:18:49AM +0000, Conor Dooley wrote:
> > T-Head now maintains some specification for their extended instructions
> > at [1], in which all instructions are prefixed "th.".
> > 
> > Follow this practice in the kernel comments.
> > 
> > [1] https://github.com/T-head-Semi/thead-extension-spec
> > 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> 
> Hey Icenowy,
> This (yet again) appears to not have made it to the list.
> It's not on patchwork, nor lore:
> https://lore.kernel.org/linux-riscv/2668919.mvXUDI8C0e@diego/T/#t
> https://lore.kernel.org/all/2668919.mvXUDI8C0e@diego/T/#t
> 
> Since you CCed lkml & not just linux-riscv, but it is not showing idk
> what's wrong..
> Your reply to me the other day came through:
> https://lore.kernel.org/all/dda144a8397a175f3ce092485f08896c9a66d232.camel@icenowy.me/

This (and the previous iteration) finally came through to the list.
I guess the pusher-of-buttons for "suspicious" mail or w/e is back to
work after Christmas. It's in patchwork now:
https://patchwork.kernel.org/project/linux-riscv/list/?series=708586

Thanks,
Conor.


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Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding

[Heiko Stübner]

Am Dienstag, 3. Januar 2023, 07:26:09 CET schrieb Icenowy Zheng:
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
> 
> Fix this in the comment and in the hardcoded instruction.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Original was on
https://lore.kernel.org/all/5894419.tdWV9SEqCh@phil/

> ---
> Included when resending:
> - Sergey's Tested-by tag.
> 
>  arch/riscv/include/asm/errata_list.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE(						\
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01001      rs1       000      00000  0001011
>   * dcache.cva rs1 (clean, virtual address)
> - *   0000001    00100      rs1       000      00000  0001011
> + *   0000001    00101      rs1       000      00000  0001011
>   *
>   * dcache.cipa rs1 (clean then invalidate, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE(						\
>   *   0000000    11001     00000      000      00000  0001011
>   */
>  #define THEAD_inval_A0	".long 0x0265000b"
> -#define THEAD_clean_A0	".long 0x0245000b"
> +#define THEAD_clean_A0	".long 0x0255000b"
>  #define THEAD_flush_A0	".long 0x0275000b"
>  #define THEAD_SYNC_S	".long 0x0190000b"
>  
> 





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Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Tue, Jan 3, 2023 at 2:26 PM Icenowy Zheng <uwu@icenowy.me> wrote:
>
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> ---
> Included when resending:
> - Sergey's Tested-by tag.
>
>  arch/riscv/include/asm/errata_list.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE(                                           \
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01001      rs1       000      00000  0001011
>   * dcache.cva rs1 (clean, virtual address)
> - *   0000001    00100      rs1       000      00000  0001011
> + *   0000001    00101      rs1       000      00000  0001011
>   *
>   * dcache.cipa rs1 (clean then invalidate, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE(                                           \
>   *   0000000    11001     00000      000      00000  0001011
>   */
>  #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
>  #define THEAD_flush_A0 ".long 0x0275000b"
>  #define THEAD_SYNC_S   ".long 0x0190000b"
>
> --
> 2.38.1
>


-- 
Best Regards
 Guo Ren

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Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding

[Icenowy Zheng]

在 2023-01-03星期二的 14:26 +0800，Icenowy Zheng写道：
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
> 
> Fix this in the comment and in the hardcoded instruction.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

Could this patch be included?

As I know, at least two C910 SoCs will be generally available, T-Head's
own TH1520 and Sophgo SG2042.

> ---
> Included when resending:
> - Sergey's Tested-by tag.
> 
>  arch/riscv/include/asm/errata_list.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/errata_list.h
> b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm
> volatile(ALTERNATIVE(                                           \
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01001      rs1       000      00000  0001011
>   * dcache.cva rs1 (clean, virtual address)
> - *   0000001    00100      rs1       000      00000  0001011
> + *   0000001    00101      rs1       000      00000  0001011
>   *
>   * dcache.cipa rs1 (clean then invalidate, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm
> volatile(ALTERNATIVE(                                           \
>   *   0000000    11001     00000      000      00000  0001011
>   */
>  #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
>  #define THEAD_flush_A0 ".long 0x0275000b"
>  #define THEAD_SYNC_S   ".long 0x0190000b"
>  

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