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boundary="===============1491702606809379710==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============1491702606809379710== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="HGsSkcCnl6i5IGAx" Content-Disposition: inline --HGsSkcCnl6i5IGAx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hey Anup, On Tue, Jan 03, 2023 at 07:44:04PM +0530, Anup Patel wrote: > We add DT bindings document for the RISC-V incoming MSI controller > (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) > specification. >=20 > Signed-off-by: Anup Patel > + The IMSIC is a per-CPU (or per-HART) device with separate interrupt fi= le > + for each privilege level (machine or supervisor). > + The device tree of a RISC-V platform will have one IMSIC device tree n= ode > + for each privilege level (machine or supervisor) which collectively de= scribe > + IMSIC interrupt files at that privilege level across CPUs (or HARTs). > +examples: > + - | > + // Example 1 (Machine-level IMSIC files with just one group): > + > + imsic_mlevel: interrupt-controller@24000000 { > + compatible =3D "riscv,qemu-imsics", "riscv,imsics"; > + interrupts-extended =3D <&cpu1_intc 11>, > + <&cpu2_intc 11>, > + <&cpu3_intc 11>, > + <&cpu4_intc 11>; > + reg =3D <0x28000000 0x4000>; > + interrupt-controller; > + #interrupt-cells =3D <0>; > + msi-controller; > + riscv,num-ids =3D <127>; > + }; > + > + - | > + // Example 2 (Supervisor-level IMSIC files with two groups): > + > + imsic_slevel: interrupt-controller@28000000 { > + compatible =3D "riscv,qemu-imsics", "riscv,imsics"; > + interrupts-extended =3D <&cpu1_intc 9>, > + <&cpu2_intc 9>, > + <&cpu3_intc 9>, > + <&cpu4_intc 9>; > + reg =3D <0x28000000 0x2000>, /* Group0 IMSICs */ > + <0x29000000 0x2000>; /* Group1 IMSICs */ > + interrupt-controller; > + #interrupt-cells =3D <0>; > + msi-controller; > + riscv,num-ids =3D <127>; > + riscv,group-index-bits =3D <1>; > + riscv,group-index-shift =3D <24>; > + }; How is, say linux, meant to know which of the per-level imsic DT nodes applies to it? I had a quick look in the driver, but could see no mechanism for it. Apologies if I missed something obvious! Thanks, Conor. --HGsSkcCnl6i5IGAx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY7YJ9gAKCRB4tDGHoIJi 0vn2AP9AbpFEPFtXjhX2Xeds9ujqOyZk3T0cfbS1mobVcSsGIQEAhYSYvxGdTD6Y DuHQBNOoJjvpsXYzq43BM95cTisFTw0= =QAG0 -----END PGP SIGNATURE----- --HGsSkcCnl6i5IGAx-- --===============1491702606809379710== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============1491702606809379710==--