From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D7CAC54EBD for ; Fri, 6 Jan 2023 21:45:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Xe8E9xdwhPKU865/iKyhq66e8IqgtLqnPiq63/RsTDA=; b=D/bX1UzdddWA43V3/rmd/cOqhs WW23x1CHK8cHpN1//oy3x96su9WAfojlnrxJMxMijz/NApGajRli4rCIFXjbXY7fCUT9uBRNsc23m D0ykojaIghoHjas0ZDv7gm9oriUbdQdoVv/G73rP6UEAgjI6ZUdO5oSbf4o9nLOdHvao/bOfdIcrC TK4YmhXkjw/ojQNaVBwV+84AeiJVfbMJO5EZ7ieY4ueCwjJ6WJhqMQ3L9Iyq0fNFdcvavtRuScrdv dlaIkfifFYHGUaP+z3cfNgIypposxJdotp/HVuD5TjE6i2khBJBmwdDGwfgmVsuhJ3RLss4LcP2Qs YkV2oVbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDuWI-00F7LF-6L; Fri, 06 Jan 2023 21:44:58 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDuWG-00F7Ju-2y for linux-riscv@lists.infradead.org; Fri, 06 Jan 2023 21:44:57 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0DDBC61F8C; Fri, 6 Jan 2023 21:44:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 23669C433EF; Fri, 6 Jan 2023 21:44:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673041493; bh=S6o14xUMpNWT1FgKozp+8Mj2OtyQejRW1OZhSS08KNM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=PaXnKMegaaP8z9ayDQcvrAUoCm6q92bglcPk8+v4XdHgqBfWpX8/c7mIncuC7ZPho 8INfXpMJNIhSCG72NGM3///9N6KJ1Rbxhg8r9i9vguk2uFn9hTbwVZx4o32zo2t5Oj kL41IACjKWCbf98FhpuXG0+S73YkTqnOLzWqb3tlRJlIHd3lakCeaCQ37G2pnUB5wQ lKFXYZ955FGncx/r01DjVLO6b2p14tp+Ho+tQqoWHFzNFS4b7KBQMFbEvhvoMJeP3A rk23L8zlMc5hO6W4stjqdZHOkpenZQtdvzPZa5BIOtVE0FkRaDu0B8/I/sJgDsQFQG cPf+lSTSscrkQ== Date: Fri, 6 Jan 2023 21:44:47 +0000 From: Conor Dooley To: Prabhakar Cc: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , "open list:RISC-V ARCHITECTURE" , open list , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar , Philipp Tomsich , Jisheng Zhang Subject: Re: [PATCH v6 3/6] riscv: errata: Add Andes alternative ports Message-ID: References: <20230106185526.260163-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20230106185526.260163-4-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 In-Reply-To: <20230106185526.260163-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230106_134456_231305_8EEFCEBE X-CRM114-Status: GOOD ( 25.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============4761099716744604112==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============4761099716744604112== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Zd9zzwISgem4Gol8" Content-Disposition: inline --Zd9zzwISgem4Gol8 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jan 06, 2023 at 06:55:23PM +0000, Prabhakar wrote: > From: Lad Prabhakar >=20 > Add required ports of the Alternative scheme for Andes CPU cores. >=20 > I/O Coherence Port (IOCP) provides an AXI interface for connecting extern= al > non-caching masters, such as DMA controllers. IOCP is a specification > option and is disabled on the Renesas RZ/Five SoC due to this reason cache > management needs a software workaround. >=20 > Signed-off-by: Lad Prabhakar > --- > v5 -> v6 > * Dropped patching alternative and now just probing IOCP >=20 > v4 -> v5 > * Sorted the Kconfig/Makefile/Switch based on Core name > * Added a comments > * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if > CMO needs to be applied. Is there a way we can access the DTB while pat= ching > as we can drop this SBI EXT ID and add a DT property instead for cmo? >=20 > RFC v3 -> v4 > * New patch > --- > arch/riscv/Kconfig.erratas | 22 +++++++++ > arch/riscv/errata/Makefile | 1 + > arch/riscv/errata/andes/Makefile | 1 + > arch/riscv/errata/andes/errata.c | 71 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/alternative.h | 3 ++ > arch/riscv/kernel/alternative.c | 5 ++ > 6 files changed, 103 insertions(+) > create mode 100644 arch/riscv/errata/andes/Makefile > create mode 100644 arch/riscv/errata/andes/errata.c >=20 > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > index 69621ae6d647..f0f0c1abd52b 100644 > --- a/arch/riscv/Kconfig.erratas > +++ b/arch/riscv/Kconfig.erratas > @@ -1,5 +1,27 @@ > menu "CPU errata selection" > =20 > +config ERRATA_ANDES > + bool "Andes AX45MP errata" > + depends on !XIP_KERNEL > + select RISCV_ALTERNATIVE > + help > + All Andes errata Kconfig depend on this Kconfig. Disabling > + this Kconfig will disable all Andes errata. Please say "Y" > + here if your platform uses Andes CPU cores. > + > + Otherwise, please say "N" here to avoid unnecessary overhead. > + > +config ERRATA_ANDES_CMO > + bool "Apply Andes cache management errata" > + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 > + select RISCV_DMA_NONCOHERENT > + default y > + help > + This will apply the cache management errata to handle the > + non-standard handling on non-coherent operations on Andes cores. > + > + If you don't know what to do here, say "Y". Ideally we would not need errata to turn this stuff on at all, but, as you pointed out to me off-list, arch_setup_dma_ops() complains if we have not set up. I'm happy to commit to trying to sort that out in follow on work w/ MPFS, since in that case it really isn't errata, and not require it for this series as you do fit that particular bill IMO. Reviewed-by: Conor Dooley Thanks, Conor. --Zd9zzwISgem4Gol8 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY7iWTwAKCRB4tDGHoIJi 0olEAPoCdBHN/hX+YSUm1Fjy2xwp6TNGBBXu8o1krE1zIfywRAD/Zgo9xhRo3YEq gijazhkKQDRtERVdc8B/eqvdErFkDgo= =DDRQ -----END PGP SIGNATURE----- --Zd9zzwISgem4Gol8-- --===============4761099716744604112== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4761099716744604112==--