From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0579FC5479D for ; Mon, 9 Jan 2023 17:20:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NiXriLDFrTgvqtPSScNvrHb23pXBJaMBY37XU7Qb1mA=; b=B1aJ+dYHWob0fi msWKl0o/309wAYmBM1w30yNFQ8Q3pBq/SuhDr8VAh6Oib/m12L2goK1qeHbw1aly4BheXR/T1z8n6 0KAl5/ui7S/JLvS6hPgE6veAnWthTVJWlVQgWiyCkBWLasM43gC/iJqIgOruXdezt7P1YXV8SXKPn VNARSPIA5MrwruVE0VvDV9TvZ87PpY2ENzhbL6LPjH5dVAkPClNfR/FNk1YyNq3aZiwKPX6YLI5oi Xf22zJrhLr5Br2VayBjDHkWy/6sVXGTRnwZfW+NriTmLwiq5jclkXSuiQmVng8dkLKTZ+/WlP/qsl 4WNAXsjUUVgKTNXR/POQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pEvoe-002sCs-9D; Mon, 09 Jan 2023 17:20:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pEvob-002sBV-D2 for linux-riscv@lists.infradead.org; Mon, 09 Jan 2023 17:20:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E193FC14; Mon, 9 Jan 2023 09:20:43 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.37.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C9DC3F587; Mon, 9 Jan 2023 09:19:59 -0800 (PST) Date: Mon, 9 Jan 2023 17:19:56 +0000 From: Mark Rutland To: guoren@kernel.org Cc: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, conor.dooley@microchip.com, heiko@sntech.de, rostedt@goodmis.org, mhiramat@kernel.org, jolsa@redhat.com, bp@suse.de, jpoimboe@kernel.org, suagrfillet@gmail.com, andy.chiu@sifive.com, e.shatokhin@yadro.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH -next V6 1/7] riscv: ftrace: Fixup panic by disabling preemption Message-ID: References: <20230107133549.4192639-1-guoren@kernel.org> <20230107133549.4192639-2-guoren@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230107133549.4192639-2-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230109_092005_578311_C768E808 X-CRM114-Status: GOOD ( 18.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Jan 07, 2023 at 08:35:43AM -0500, guoren@kernel.org wrote: > From: Andy Chiu > > In RISCV, we must use an AUIPC + JALR pair to encode an immediate, > forming a jump that jumps to an address over 4K. This may cause errors > if we want to enable kernel preemption and remove dependency from > patching code with stop_machine(). For example, if a task was switched > out on auipc. And, if we changed the ftrace function before it was > switched back, then it would jump to an address that has updated 11:0 > bits mixing with previous XLEN:12 part. > > p: patched area performed by dynamic ftrace > ftrace_prologue: > p| REG_S ra, -SZREG(sp) > p| auipc ra, 0x? ------------> preempted > ... > change ftrace function > ... > p| jalr -?(ra) <------------- switched back > p| REG_L ra, -SZREG(sp) > func: > xxx > ret What happens on SMP but not !PREEMPTION; can't a CPU be in the middle of this while you're patching the sequence? Do you have any guarantee as to the atomicity and ordering of instruction fetches? Thanks, Mark. > > Fixes: afc76b8b8011 ("riscv: Using PATCHABLE_FUNCTION_ENTRY instead of MCOUNT") > Signed-off-by: Andy Chiu > Signed-off-by: Guo Ren > --- > arch/riscv/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e2b656043abf..ee0d39b26794 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -138,7 +138,7 @@ config RISCV > select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE > select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL > select HAVE_FUNCTION_GRAPH_TRACER > - select HAVE_FUNCTION_TRACER if !XIP_KERNEL > + select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !PREEMPTION > > config ARCH_MMAP_RND_BITS_MIN > default 18 if 64BIT > -- > 2.36.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv