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From: Conor Dooley <conor.dooley@microchip.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: <linux-riscv@lists.infradead.org>,
	<kvm-riscv@lists.infradead.org>,
	'Atish Patra ' <atishp@rivosinc.com>,
	'Jisheng Zhang ' <jszhang@kernel.org>,
	'Palmer Dabbelt ' <palmer@dabbelt.com>,
	'Albert Ou ' <aou@eecs.berkeley.edu>,
	'Paul Walmsley ' <paul.walmsley@sifive.com>,
	'Heiko Stuebner ' <heiko@sntech.de>,
	'Anup Patel ' <apatel@ventanamicro.com>,
	Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Document cboz-block-size
Date: Mon, 23 Jan 2023 08:10:35 +0000	[thread overview]
Message-ID: <Y85A+3MW2N/jPTHH@wendy> (raw)
In-Reply-To: <20230122191328.1193885-3-ajones@ventanamicro.com>


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Hey,

On Sun, Jan 22, 2023 at 08:13:24PM +0100, Andrew Jones wrote:
> The Zicboz operates on a block-size defined for the cpu-core,
> which does not necessarily match other cache-sizes used.
> 
> So add the necessary property for the system to know the core's
> block-size.
> 
> Cc: Rob Herring <robh@kernel.org>

FYI bindings need to be CC Krzysztof & the devicetree list too.

> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c6720764e765..f4ee70f8e1cf 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -72,6 +72,11 @@ properties:
>      description:
>        The blocksize in bytes for the Zicbom cache operations.
>  
> +  riscv,cboz-block-size:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      The blocksize in bytes for the Zicboz cache operations.

Do you think hardware that has different Zicboz versus Zicbom block
sizes is going to be common, or would we benefit from just defaulting
the Zicboz size to the Zicbom one?

Either way,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.


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  reply	other threads:[~2023-01-23  8:11 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-22 19:13 [PATCH v2 0/6] RISC-V: Apply Zicboz to clear_page Andrew Jones
2023-01-22 19:13 ` [PATCH v2 1/6] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Andrew Jones
2023-01-22 19:13 ` [PATCH v2 2/6] dt-bindings: riscv: Document cboz-block-size Andrew Jones
2023-01-23  8:10   ` Conor Dooley [this message]
2023-01-23  9:44     ` Andrew Jones
2023-01-23 15:57       ` Krzysztof Kozlowski
2023-01-23 14:33   ` Rob Herring
2023-01-23 15:54     ` Andrew Jones
2023-01-23 18:25       ` Conor Dooley
2023-01-24  5:35         ` Andrew Jones
2023-01-22 19:13 ` [PATCH v2 3/6] RISC-V: Add Zicboz detection and block size parsing Andrew Jones
2023-01-22 19:13 ` [PATCH v2 4/6] RISC-V: Use Zicboz in clear_page when available Andrew Jones
2023-01-23 11:42   ` Conor Dooley
2023-01-22 19:13 ` [PATCH v2 5/6] RISC-V: KVM: Provide UAPI for Zicboz block size Andrew Jones
2023-01-22 19:13 ` [PATCH v2 6/6] RISC-V: KVM: Expose Zicboz to the guest Andrew Jones

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