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d="asc'?scan'208";a="193409181" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jan 2023 01:11:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 23 Jan 2023 01:11:00 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16 via Frontend Transport; Mon, 23 Jan 2023 01:10:58 -0700 Date: Mon, 23 Jan 2023 08:10:35 +0000 From: Conor Dooley To: Andrew Jones CC: , , 'Atish Patra ' , 'Jisheng Zhang ' , 'Palmer Dabbelt ' , 'Albert Ou ' , 'Paul Walmsley ' , 'Heiko Stuebner ' , 'Anup Patel ' , Rob Herring Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Document cboz-block-size Message-ID: References: <20230122191328.1193885-1-ajones@ventanamicro.com> <20230122191328.1193885-3-ajones@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20230122191328.1193885-3-ajones@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230123_001105_750655_04F11DB2 X-CRM114-Status: GOOD ( 16.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1024799616251640014==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============1024799616251640014== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Ek/NdeMhlk/2U4U0" Content-Disposition: inline --Ek/NdeMhlk/2U4U0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hey, On Sun, Jan 22, 2023 at 08:13:24PM +0100, Andrew Jones wrote: > The Zicboz operates on a block-size defined for the cpu-core, > which does not necessarily match other cache-sizes used. >=20 > So add the necessary property for the system to know the core's > block-size. >=20 > Cc: Rob Herring FYI bindings need to be CC Krzysztof & the devicetree list too. > Signed-off-by: Andrew Jones > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Document= ation/devicetree/bindings/riscv/cpus.yaml > index c6720764e765..f4ee70f8e1cf 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -72,6 +72,11 @@ properties: > description: > The blocksize in bytes for the Zicbom cache operations. > =20 > + riscv,cboz-block-size: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The blocksize in bytes for the Zicboz cache operations. Do you think hardware that has different Zicboz versus Zicbom block sizes is going to be common, or would we benefit from just defaulting the Zicboz size to the Zicbom one? Either way, Reviewed-by: Conor Dooley Thanks, Conor. --Ek/NdeMhlk/2U4U0 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY85A+wAKCRB4tDGHoIJi 0ke7AQCGPJvwCpVHyhuvGR/MLJdfT0M4vPc1ZgK+lmvyu8YRAAEAoMVeTGxyZMRz uS/apb4qDM6fQV42ru6dBfsl2KU1uQo= =jJXh -----END PGP SIGNATURE----- --Ek/NdeMhlk/2U4U0-- --===============1024799616251640014== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============1024799616251640014==--