Re: [PATCH v1 1/2] riscv: Kconfig: Allow RV32 to build with no MMU

kernel test robot
2023-01-20T07:34:43Z

Hi Jesse,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on linus/master]
[also build test ERROR on v6.2-rc4 next-20230120]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Jesse-Taube/riscv-Kconfig-Allow-RV32-to-build-with-no-MMU/20230119-132822
patch link: https://lore.kernel.org/r/20230119052642.1112171-2-Mr.Bossman075%40gmail.com
patch subject: [PATCH v1 1/2] riscv: Kconfig: Allow RV32 to build with no MMU
config: riscv-randconfig-c003-20230119 (https://download.01.org/0day-ci/archive/20230120/202301201538.zNlqgE4L-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/4c6876d890ddeab1fb2cb42889027c6d1dbdd02f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jesse-Taube/riscv-Kconfig-Allow-RV32-to-build-with-no-MMU/20230119-132822
git checkout 4c6876d890ddeab1fb2cb42889027c6d1dbdd02f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=riscv olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

riscv32-linux-ld: drivers/clk/clk-k210.o: in function `k210_pll_get_rate':
>> drivers/clk/clk-k210.c:498: undefined reference to `__udivdi3'

vim +498 drivers/clk/clk-k210.c

c6ca7616f7d5c2 Damien Le Moal 2021-02-10 480
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 481 static unsigned long k210_pll_get_rate(struct clk_hw *hw,
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 482 unsigned long parent_rate)
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 483 {
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 484 struct k210_pll *pll = to_k210_pll(hw);
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 485 u32 reg = readl(pll->reg);
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 486 u32 r, f, od;
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 487
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 488 if (reg & K210_PLL_BYPASS)
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 489 return parent_rate;
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 490
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 491 if (!(reg & K210_PLL_PWRD))
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 492 return 0;
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 493
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 494 r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 495 f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 496 od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 497
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 @498 return (u64)parent_rate * f / (r * od);
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 499 }
c6ca7616f7d5c2 Damien Le Moal 2021-02-10 500

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