Re: [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap

Björn Töpel
2023-02-08T09:20:41Z

Vineet Gupta <vineetg@rivosinc.com> writes:

> Hi Andy,
>
> On 1/25/23 06:20, Andy Chiu wrote:
>> +static bool insn_is_vector(u32 insn_buf)
>> +{
>> + u32 opcode = insn_buf & __INSN_OPCODE_MASK;
>> + /*
>> + * All V-related instructions, including CSR operations are 4-Byte. So,
>> + * do not handle if the instruction length is not 4-Byte.
>> + */
>> + if (unlikely(GET_INSN_LENGTH(insn_buf) != 4))
>> + return false;
>> + if (opcode == OPCODE_VECTOR) {
>> + return true;
>> + } else if (opcode == OPCODE_LOADFP || opcode == OPCODE_STOREFP) {
>> + u32 width = EXTRACT_LOAD_STORE_FP_WIDTH(insn_buf);
>> +
>> + if (width == LSFP_WIDTH_RVV_8 || width == LSFP_WIDTH_RVV_16 ||
>> + width == LSFP_WIDTH_RVV_32 || width == LSFP_WIDTH_RVV_64)
>> + return true;
>
> What is the purpose of checking FP opcodes here ?

From [1]: "The instructions in the vector extension fit under two
existing major opcodes (LOAD-FP and STORE-FP) and one new major opcode
(OP-V)."

[2] highlights the width encoding.

(And Zvamo is out from the spec, which used AMO,0x2f)

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#5-vector-instruction-formats
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#73-vector-loadstore-width-encoding