From: Conor Dooley <conor.dooley@microchip.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: <linux-kernel@vger.kernel.org>, Anup Patel <anup@brainfault.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Eric Lin <eric.lin@sifive.com>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>, <kvm-riscv@lists.infradead.org>,
<kvm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v4 08/14] RISC-V: KVM: Add SBI PMU extension support
Date: Thu, 2 Feb 2023 07:52:37 +0000 [thread overview]
Message-ID: <Y9trxX9hj6/pi1b1@wendy> (raw)
In-Reply-To: <20230201231250.3806412-9-atishp@rivosinc.com>
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Hey Atish,
On Wed, Feb 01, 2023 at 03:12:44PM -0800, Atish Patra wrote:
> SBI PMU extension allows KVM guests to configure/start/stop/query about
> the PMU counters in virtualized enviornment as well.
>
> In order to allow that, KVM implements the entire SBI PMU extension.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Could complaints from CI for you:
+ 1 ../arch/riscv/kvm/vcpu_sbi_pmu.c:73:15: warning: no previous prototype for 'kvm_sbi_ext_pmu_probe' [-Wmissing-prototypes]
+ 1 ../arch/riscv/kvm/vcpu_sbi_pmu.c:73:15: warning: symbol 'kvm_sbi_ext_pmu_probe' was not declared. Should it be static?
+ 1 ../arch/riscv/kvm/vcpu_sbi_pmu.c:80:37: warning: symbol 'vcpu_sbi_ext_pmu' was not declared. Should it be static?
Thanks,
Conor.
> ---
> arch/riscv/kvm/Makefile | 2 +-
> arch/riscv/kvm/vcpu_sbi.c | 11 +++++
> arch/riscv/kvm/vcpu_sbi_pmu.c | 85 +++++++++++++++++++++++++++++++++++
> 3 files changed, 97 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/kvm/vcpu_sbi_pmu.c
>
> diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile
> index 5de1053..278e97c 100644
> --- a/arch/riscv/kvm/Makefile
> +++ b/arch/riscv/kvm/Makefile
> @@ -25,4 +25,4 @@ kvm-y += vcpu_sbi_base.o
> kvm-y += vcpu_sbi_replace.o
> kvm-y += vcpu_sbi_hsm.o
> kvm-y += vcpu_timer.o
> -kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_pmu.o
> +kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_pmu.o vcpu_sbi_pmu.o
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index fe2897e..15fde15 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -20,6 +20,16 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
> };
> #endif
>
> +#ifdef CONFIG_RISCV_PMU_SBI
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu;
> +#else
> +static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu = {
> + .extid_start = -1UL,
> + .extid_end = -1UL,
> + .handler = NULL,
> +};
> +#endif
> +
> static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_v01,
> &vcpu_sbi_ext_base,
> @@ -28,6 +38,7 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_rfence,
> &vcpu_sbi_ext_srst,
> &vcpu_sbi_ext_hsm,
> + &vcpu_sbi_ext_pmu,
> &vcpu_sbi_ext_experimental,
> &vcpu_sbi_ext_vendor,
> };
> diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c
> new file mode 100644
> index 0000000..e028b0a
> --- /dev/null
> +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Rivos Inc
> + *
> + * Authors:
> + * Atish Patra <atishp@rivosinc.com>
> + */
> +
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/kvm_host.h>
> +#include <asm/csr.h>
> +#include <asm/sbi.h>
> +#include <asm/kvm_vcpu_sbi.h>
> +
> +static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> + struct kvm_vcpu_sbi_return *retdata)
> +{
> + int ret = 0;
> + struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> + struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
> + unsigned long funcid = cp->a6;
> + uint64_t temp;
> +
> + /* Return not supported if PMU is not initialized */
> + if (!kvpmu->init_done)
> + return -EINVAL;
> +
> + switch (funcid) {
> + case SBI_EXT_PMU_NUM_COUNTERS:
> + ret = kvm_riscv_vcpu_pmu_num_ctrs(vcpu, retdata);
> + break;
> + case SBI_EXT_PMU_COUNTER_GET_INFO:
> + ret = kvm_riscv_vcpu_pmu_ctr_info(vcpu, cp->a0, retdata);
> + break;
> + case SBI_EXT_PMU_COUNTER_CFG_MATCH:
> +#if defined(CONFIG_32BIT)
> + temp = ((uint64_t)cp->a5 << 32) | cp->a4;
> +#else
> + temp = cp->a4;
> +#endif
> + /*
> + * This can fail if perf core framework fails to create an event.
> + * Forward the error to the user space because its an error happened
> + * within host kernel. The other option would be convert this to
> + * an SBI error and forward to the guest.
> + */
> + ret = kvm_riscv_vcpu_pmu_ctr_cfg_match(vcpu, cp->a0, cp->a1,
> + cp->a2, cp->a3, temp, retdata);
> + break;
> + case SBI_EXT_PMU_COUNTER_START:
> +#if defined(CONFIG_32BIT)
> + temp = ((uint64_t)cp->a4 << 32) | cp->a3;
> +#else
> + temp = cp->a3;
> +#endif
> + ret = kvm_riscv_vcpu_pmu_ctr_start(vcpu, cp->a0, cp->a1, cp->a2,
> + temp, retdata);
> + break;
> + case SBI_EXT_PMU_COUNTER_STOP:
> + ret = kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdata);
> + break;
> + case SBI_EXT_PMU_COUNTER_FW_READ:
> + ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata);
> + break;
> + default:
> + retdata->err_val = SBI_ERR_NOT_SUPPORTED;
> + }
> +
> + return ret;
> +}
> +
> +unsigned long kvm_sbi_ext_pmu_probe(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
> +
> + return kvpmu->init_done;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu = {
> + .extid_start = SBI_EXT_PMU,
> + .extid_end = SBI_EXT_PMU,
> + .handler = kvm_sbi_ext_pmu_handler,
> + .probe = kvm_sbi_ext_pmu_probe,
> +};
> --
> 2.25.1
>
>
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next prev parent reply other threads:[~2023-02-02 7:53 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-01 23:12 [PATCH v4 00/14] KVM perf support Atish Patra
2023-02-01 23:12 ` [PATCH v4 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra
2023-02-02 14:59 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra
2023-02-01 23:12 ` [PATCH v4 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra
2023-02-02 4:00 ` Anup Patel
2023-02-02 15:01 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra
2023-02-02 15:14 ` Andrew Jones
2023-02-02 15:16 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra
2023-02-02 15:26 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra
2023-02-02 4:01 ` Anup Patel
2023-02-02 8:52 ` Anup Patel
2023-02-02 15:56 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra
2023-02-02 4:02 ` Anup Patel
2023-02-02 11:33 ` Conor Dooley
2023-02-03 8:04 ` Atish Patra
2023-02-03 8:08 ` Conor Dooley
2023-02-02 17:03 ` Andrew Jones
2023-02-03 8:47 ` Atish Patra
2023-02-05 7:37 ` Atish Patra
2023-02-06 9:22 ` Andrew Jones
2023-02-06 11:39 ` Andrew Jones
2023-02-07 9:20 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra
2023-02-02 7:52 ` Conor Dooley [this message]
2023-02-02 17:29 ` Andrew Jones
2023-02-03 9:07 ` Atish Patra
2023-02-01 23:12 ` [PATCH v4 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra
2023-02-02 17:30 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra
2023-02-01 23:12 ` [PATCH v4 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra
2023-02-01 23:12 ` [PATCH v4 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra
2023-02-02 18:44 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 13/14] RISC-V: KVM: Support firmware events Atish Patra
2023-02-02 11:40 ` Conor Dooley
2023-02-03 10:14 ` Andrew Jones
2023-02-01 23:12 ` [PATCH v4 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra
2023-02-02 18:48 ` Andrew Jones
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