[PATCH] RISC-V: Only provide the single-letter extensions in HWCAP

[PATCH] RISC-V: Only provide the single-letter extensions in HWCAP

[Palmer Dabbelt]

The recent refactoring led to us leaking some HWCAP bits to userspace
that didn't make much sense.  With any luck we'll have a better scheme
soon, but for now just mask off those bits to avoid polluting userspace.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/asm/elf.h   | 10 ++++++----
 arch/riscv/include/asm/hwcap.h |  8 --------
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index e7acffdf21d2..30e7d2455960 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -14,6 +14,7 @@
 #include <asm/auxvec.h>
 #include <asm/byteorder.h>
 #include <asm/cacheinfo.h>
+#include <asm/hwcap.h>
 
 /*
  * These are used to set parameters in the core dumps.
@@ -59,12 +60,13 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr);
 #define STACK_RND_MASK		(0x3ffff >> (PAGE_SHIFT - 12))
 #endif
 #endif
+
 /*
- * This yields a mask that user programs can use to figure out what
- * instruction set this CPU supports.  This could be done in user space,
- * but it's not easy, and we've already done it here.
+ * Provides information on the availiable set of ISA extensions to userspace,
+ * via a bitmap that coorespends to each single-letter ISA extension.  This is
+ * essentially defunct, but will remain for compatibility with userspace.
  */
-#define ELF_HWCAP	(elf_hwcap)
+#define ELF_HWCAP	(elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1))
 extern unsigned long elf_hwcap;
 
 /*
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index ee9c80fe0062..831bebacb7fb 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -52,18 +52,10 @@
 
 #include <linux/jump_label.h>
 
-/*
- * This yields a mask that user programs can use to figure out what
- * instruction set this cpu supports.
- */
-#define ELF_HWCAP		(elf_hwcap)
-
 enum {
 	CAP_HWCAP = 1,
 };
 
-extern unsigned long elf_hwcap;
-
 struct riscv_isa_ext_data {
 	/* Name of the extension displayed to userspace via /proc/cpuinfo */
 	char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
-- 
2.39.0


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Re: [PATCH] RISC-V: Only provide the single-letter extensions in HWCAP

[Conor Dooley]

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On Thu, Feb 02, 2023 at 03:38:32PM -0800, Palmer Dabbelt wrote:
> The recent refactoring led to us leaking some HWCAP bits to userspace
> that didn't make much sense.  With any luck we'll have a better scheme
> soon, but for now just mask off those bits to avoid polluting userspace.
> 
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  arch/riscv/include/asm/elf.h   | 10 ++++++----
>  arch/riscv/include/asm/hwcap.h |  8 --------
>  2 files changed, 6 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
> index e7acffdf21d2..30e7d2455960 100644
> --- a/arch/riscv/include/asm/elf.h
> +++ b/arch/riscv/include/asm/elf.h
> @@ -14,6 +14,7 @@
>  #include <asm/auxvec.h>
>  #include <asm/byteorder.h>
>  #include <asm/cacheinfo.h>
> +#include <asm/hwcap.h>
>  
>  /*
>   * These are used to set parameters in the core dumps.
> @@ -59,12 +60,13 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr);
>  #define STACK_RND_MASK		(0x3ffff >> (PAGE_SHIFT - 12))
>  #endif
>  #endif
> +
>  /*
> - * This yields a mask that user programs can use to figure out what
> - * instruction set this CPU supports.  This could be done in user space,
> - * but it's not easy, and we've already done it here.
> + * Provides information on the availiable set of ISA extensions to userspace,
> + * via a bitmap that coorespends to each single-letter ISA extension.  This is
> + * essentially defunct, but will remain for compatibility with userspace.
>   */
> -#define ELF_HWCAP	(elf_hwcap)
> +#define ELF_HWCAP	(elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1))

Should that not be a GENMASK, or is there a reason not to use that here?
Away from a setup where I can poke at it though, so, since you say this
has only been exported in for-next, preventing us running out of hwcap
sounds like a great idea.

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

>  extern unsigned long elf_hwcap;
>  
>  /*
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index ee9c80fe0062..831bebacb7fb 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -52,18 +52,10 @@
>  
>  #include <linux/jump_label.h>
>  
> -/*
> - * This yields a mask that user programs can use to figure out what
> - * instruction set this cpu supports.
> - */
> -#define ELF_HWCAP		(elf_hwcap)
> -
>  enum {
>  	CAP_HWCAP = 1,
>  };
>  
> -extern unsigned long elf_hwcap;
> -
>  struct riscv_isa_ext_data {
>  	/* Name of the extension displayed to userspace via /proc/cpuinfo */
>  	char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
> -- 
> 2.39.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

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Re: [PATCH] RISC-V: Only provide the single-letter extensions in HWCAP

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Thu,  2 Feb 2023 15:38:32 -0800 you wrote:
> The recent refactoring led to us leaking some HWCAP bits to userspace
> that didn't make much sense.  With any luck we'll have a better scheme
> soon, but for now just mask off those bits to avoid polluting userspace.
> 
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  arch/riscv/include/asm/elf.h   | 10 ++++++----
>  arch/riscv/include/asm/hwcap.h |  8 --------
>  2 files changed, 6 insertions(+), 12 deletions(-)

Here is the summary with links:
  - RISC-V: Only provide the single-letter extensions in HWCAP
    https://git.kernel.org/riscv/c/2350bd192fa2

You are awesome, thank you!
-- 
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