From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A583EC433ED for ; Wed, 7 Apr 2021 16:01:09 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2B0661132 for ; Wed, 7 Apr 2021 16:01:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E2B0661132 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9PsHxczVhWZ/Ea9YoSzvhPV2w+DBzJNKkwVBjETlgnA=; b=OXuXp857+V2JlmdSRkQYMdqtg dgpwnWtaUVotMZIzzn8rVhriFjmqrLJgSqu7QRrzXYGNP7WC3/Mi1pl6T11+aQ8EKhY0zJCXfLRFt 7HSqIFsOmXVXa/c6y0t8jD14Z8qagWyPZvFqU/h28jXSkd4RHufO5nS3lFBruxxWhsmk4P1nzxZsb eeSnNha1nkNI9ntK171FapLiGMuVcNEvn544OzR93vPfhG/2Rqx5RscFqVi2vVGNXbTBdf/g2mTpn fwoezEloUSUOa2DStie6Vmcby4KK8Tlz1ja5rI5WE0l7VEeVuuFpIOGD6SR5oXnlh0VIjLgqy7feA k5Etc1pAA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lUAbl-005NNt-Sj; Wed, 07 Apr 2021 16:00:45 +0000 Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.94 #2 (Red Hat Linux)) id 1lUAbH-005NDW-Kw; Wed, 07 Apr 2021 16:00:15 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 002B73001FB; Wed, 7 Apr 2021 18:00:14 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id E298B2BF09269; Wed, 7 Apr 2021 18:00:14 +0200 (CEST) Date: Wed, 7 Apr 2021 18:00:14 +0200 From: Peter Zijlstra To: Christoph =?iso-8859-1?Q?M=FCllner?= Cc: Christoph Hellwig , Guo Ren , linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Waiman Long , Arnd Bergmann , Anup Patel Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 Message-ID: References: <1616868399-82848-4-git-send-email-guoren@kernel.org> <20210407094224.GA3393992@infradead.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph M=FCllner wrote: > RISC-V defines LR/SC loops consisting of up to 16 instructions as > constrained LR/SC loops. Such constrained LR/SC loops provide the > required forward guarantees, that are expected (similar to what other > architectures, like AArch64, have). The text quoted by others didn't seem to say such a thing, but whatever. > What RISC-V does not have is sub-word atomics and if required, we > would have to implement them as LL/SC sequences. And yes, using atomic > instructions is preferred over using LL/SC, (psudo asm, can't be bothered to figure out the actual syntax) # setup r_and_mask, r_or_mask .L1 LL r, [word] AND r, r, r_and_mask OR r, r, r_or_mask SC r, [word] JNE .L1 is what you need for LL/SC based xchg16, that's less than 16 instructions. If RISC-V guarantees fwd progress on that, good, write it like that and lets end this thread. The fact that this is apparently hard, is not good. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv