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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id k26sm596627otp.42.2021.10.26.11.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 11:57:46 -0700 (PDT) Received: (nullmailer pid 3030040 invoked by uid 1000); Tue, 26 Oct 2021 18:57:45 -0000 Date: Tue, 26 Oct 2021 13:57:45 -0500 From: Rob Herring To: Atish Patra Cc: linux-kernel@vger.kernel.org, Anup Patel , David Abdurachmanov , devicetree@vger.kernel.org, Greentime Hu , Guo Ren , Heinrich Schuchardt , Jonathan Corbet , linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Nick Kossifidis , Palmer Dabbelt , Paul Walmsley , Vincent Chen Subject: Re: [v4 06/11] dt-binding: pmu: Add RISC-V PMU DT bindings Message-ID: References: <20211025195350.242914-1-atish.patra@wdc.com> <20211025195350.242914-7-atish.patra@wdc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211025195350.242914-7-atish.patra@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211026_115748_290353_106540D0 X-CRM114-Status: GOOD ( 20.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Oct 25, 2021 at 12:53:45PM -0700, Atish Patra wrote: > This patch adds the DT bindings for RISC-V PMU driver. It also defines > the interrupt related properties to allow counter overflow interrupt. > > Signed-off-by: Atish Patra > --- > .../devicetree/bindings/perf/riscv,pmu.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml > > diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml > new file mode 100644 > index 000000000000..497caad63f16 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pmu/riscv,pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V PMU > + > +maintainers: > + - Atish Patra > + > +description: > + The "Sscofpmf" extension allows the RISC-V PMU counters to overflow and > + generate a local interrupt so that event sampling can be done from user-space. > + The above said ISA extension is an optional extension to maintain backward > + compatibility and will be included in privilege specification v1.12 . That's > + why the interrupt property is marked as optional. The platforms with sscofpmf > + extension should add this property to enable event sampling. > + The device tree node with the compatible string is mandatory for any platform > + that wants to use pmu counter start/stop methods using SBI PMU extension. > + > +properties: > + compatible: > + enum: > + - riscv,pmu Only 1 version? Every implementation detail is discoverable in other ways? > + > + description: > + Should be "riscv,pmu". Don't write free form text of what the schema says. > + > + interrupts-extended: > + minItems: 1 > + maxItems: 4095 > + > +additionalProperties: false > + > +required: > + - None > +optional: No a json-schema keyword. > + - compatible > + - interrupts-extended > + > +examples: > + - | > + pmu { > + compatible = "riscv,pmu"; > + interrupts-extended = <&cpu0intc 13>, > + <&cpu1intc 13>, > + <&cpu2intc 13>, > + <&cpu3intc 13>; > + }; > +... > -- > 2.31.1 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv