From: Andrew Lunn <andrew@lunn.ch>
To: Conor.Dooley@microchip.com
Cc: palmer@rivosinc.com, apatel@ventanamicro.com,
netdev@vger.kernel.org, Nicolas.Ferre@microchip.com,
Claudiu.Beznea@microchip.com, linux@armlinux.org.uk,
hkallweit1@gmail.com, linux-riscv@lists.infradead.org
Subject: Re: riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1
Date: Tue, 5 Apr 2022 17:04:40 +0200 [thread overview]
Message-ID: <YkxaiEbHwduhS2+p@lunn.ch> (raw)
In-Reply-To: <9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com>
> [ 2.818894] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL)
> [ 2.828915] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
> [11.045411] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
> [11.053247] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
You have a multi-part link. You need that the PHY reports the line
side is up. Put some printk in genphy_update_link() and look at
phydev->link. You also need that the SGMII link between the PHY and
the SoC is up. That is a bit harder to see, but try adding #define
DEBUG at the top of phylink.c and phy.c so you get additional debug
prints for the state machines.
Andrew
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next prev parent reply other threads:[~2022-04-05 15:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-05 13:05 riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1 Conor.Dooley
2022-04-05 13:25 ` Andrew Lunn
2022-04-05 14:18 ` Conor.Dooley
2022-04-05 14:41 ` Conor.Dooley
2022-04-05 14:49 ` Andrew Lunn
2022-04-05 14:56 ` Andrew Lunn
2022-04-05 15:04 ` Andrew Lunn [this message]
2022-04-05 16:25 ` Conor Dooley
2022-04-06 8:36 ` Conor.Dooley
2022-04-07 14:30 ` Conor.Dooley
2022-04-05 15:53 ` Russell King (Oracle)
2022-04-05 16:56 ` Palmer Dabbelt
2022-04-05 17:23 ` Conor Dooley
2022-04-05 18:06 ` Andrew Lunn
2022-04-05 18:35 ` Conor Dooley
2022-04-05 16:58 ` Conor Dooley
2022-04-05 18:55 ` Russell King (Oracle)
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