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[66.111.4.227]) by smtp.gmail.com with ESMTPSA id b126-20020a37b284000000b0069a11927e57sm1683932qkf.101.2022.04.14.18.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Apr 2022 18:09:40 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailauth.nyi.internal (Postfix) with ESMTP id 56D2A27C0054; Thu, 14 Apr 2022 21:09:39 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Thu, 14 Apr 2022 21:09:39 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrudelgedggeefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepfffhvffukfhfgggtuggjsehgtderredttddvnecuhfhrohhmpeeuohhquhhn ucfhvghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrfgrth htvghrnhepueehjeejieevueeuteeileeuvddvvedvieeltddtudekgeegueelvddtkeet tdevnecuffhomhgrihhnpehkvghrnhgvlhdrohhrghenucevlhhushhtvghrufhiiigvpe dtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegsohhquhhnodhmvghsmhhtphgruhhthhhp vghrshhonhgrlhhithihqdeiledvgeehtdeigedqudejjeekheehhedvqdgsohhquhhnrd hfvghngheppehgmhgrihhlrdgtohhmsehfihigmhgvrdhnrghmvg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 14 Apr 2022 21:09:35 -0400 (EDT) Date: Fri, 15 Apr 2022 09:09:29 +0800 From: Boqun Feng To: Palmer Dabbelt Cc: Arnd Bergmann , heiko@sntech.de, guoren@kernel.org, shorne@gmail.com, peterz@infradead.org, mingo@redhat.com, Will Deacon , longman@redhat.com, jonas@southpole.se, stefan.kristiansson@saunalahti.fi, Paul Walmsley , Palmer Dabbelt , aou@eecs.berkeley.edu, macro@orcam.me.uk, Greg KH , sudipm.mukherjee@gmail.com, wangkefeng.wang@huawei.com, jszhang@kernel.org, linux-csky@vger.kernel.org, linux-kernel@vger.kernel.org, openrisc@lists.librecores.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v3 1/7] asm-generic: ticket-lock: New generic ticket-based spinlock Message-ID: References: <20220414220214.24556-1-palmer@rivosinc.com> <20220414220214.24556-2-palmer@rivosinc.com> MIME-Version: 1.0 In-Reply-To: <20220414220214.24556-2-palmer@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220414_180943_538291_B5BBD67A X-CRM114-Status: GOOD ( 28.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============4753929597722401310==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============4753929597722401310== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="vliStJTlDzun4Idq" Content-Disposition: inline --vliStJTlDzun4Idq Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Thu, Apr 14, 2022 at 03:02:08PM -0700, Palmer Dabbelt wrote: > From: Peter Zijlstra >=20 > This is a simple, fair spinlock. Specifically it doesn't have all the > subtle memory model dependencies that qspinlock has, which makes it more > suitable for simple systems as it is more likely to be correct. It is > implemented entirely in terms of standard atomics and thus works fine > without any arch-specific code. >=20 > This replaces the existing asm-generic/spinlock.h, which just errored > out on SMP systems. >=20 > Signed-off-by: Peter Zijlstra (Intel) > Signed-off-by: Palmer Dabbelt > --- > include/asm-generic/spinlock.h | 85 +++++++++++++++++++++++++--- > include/asm-generic/spinlock_types.h | 17 ++++++ > 2 files changed, 94 insertions(+), 8 deletions(-) > create mode 100644 include/asm-generic/spinlock_types.h >=20 > diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinloc= k.h > index adaf6acab172..ca829fcb9672 100644 > --- a/include/asm-generic/spinlock.h > +++ b/include/asm-generic/spinlock.h > @@ -1,12 +1,81 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > -#ifndef __ASM_GENERIC_SPINLOCK_H > -#define __ASM_GENERIC_SPINLOCK_H > + > /* > - * You need to implement asm/spinlock.h for SMP support. The generic > - * version does not handle SMP. > + * 'Generic' ticket-lock implementation. > + * > + * It relies on atomic_fetch_add() having well defined forward progress > + * guarantees under contention. If your architecture cannot provide this= , stick > + * to a test-and-set lock. > + * > + * It also relies on atomic_fetch_add() being safe vs smp_store_release(= ) on a > + * sub-word of the value. This is generally true for anything LL/SC alth= ough > + * you'd be hard pressed to find anything useful in architecture specifi= cations > + * about this. If your architecture cannot do this you might be better o= ff with > + * a test-and-set. > + * > + * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc an= d hence > + * uses atomic_fetch_add() which is SC to create an RCsc lock. > + * > + * The implementation uses smp_cond_load_acquire() to spin, so if the > + * architecture has WFE like instructions to sleep instead of poll for w= ord > + * modifications be sure to implement that (see ARM64 for example). > + * > */ > -#ifdef CONFIG_SMP > -#error need an architecture specific asm/spinlock.h > -#endif > =20 > -#endif /* __ASM_GENERIC_SPINLOCK_H */ > +#ifndef __ASM_GENERIC_TICKET_LOCK_H > +#define __ASM_GENERIC_TICKET_LOCK_H > + > +#include > +#include > + > +static __always_inline void arch_spin_lock(arch_spinlock_t *lock) > +{ > + u32 val =3D atomic_fetch_add(1<<16, lock); /* SC, gives us RCsc */ > + u16 ticket =3D val >> 16; > + > + if (ticket =3D=3D (u16)val) > + return; > + > + atomic_cond_read_acquire(lock, ticket =3D=3D (u16)VAL); Looks like my follow comment is missing: https://lore.kernel.org/lkml/YjM+P32I4fENIqGV@boqun-archlinux/ Basically, I suggested that 1) instead of "SC", use "fully-ordered" as that's a complete definition in our atomic API ("RCsc" is fine), 2) introduce a RCsc atomic_cond_read_acquire() or add a full barrier here to make arch_spin_lock() RCsc otherwise arch_spin_lock() is RCsc on fastpath but RCpc on slowpath. Regards, Boqun > +} > + > +static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock) > +{ > + u32 old =3D atomic_read(lock); > + > + if ((old >> 16) !=3D (old & 0xffff)) > + return false; > + > + return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */ > +} > + [...] --vliStJTlDzun4Idq Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEj5IosQTPz8XU1wRHSXnow7UH+rgFAmJYxcUACgkQSXnow7UH +rihtgf/QlwBFoAeUTlH4MhKKy3Fr6WrwXq/WIgA71uyveBP8XeJF92iatARzevG wKLiIQzO4VzrpLJ8Ydy+o4ia1xb+nCqwVE0MD2oqPjxwvvyi/7HxZFBI4iq3PZHm 3FRwaGPnNrQGfFmyjM/byXc6uQ/NlPY65rZJcR5wS5j14F5NXAUjOBXrWVQT8nBU livaSZhbWwyn5oEnzsy/G/oAeD16LIJbjF2pQyX3FPtd1sIlIdOCjWN3TSIM2e2+ enFK5X7w489U+pKfVIOygTWHe95dd9JNsEsSyDmXkTJQnn/cCbYNfI+BR/H2Hc9G HyLCBV1KDHETDNQ25uo2WoTdfceyNQ== =T3Uh -----END PGP SIGNATURE----- --vliStJTlDzun4Idq-- --===============4753929597722401310== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4753929597722401310==--