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From: Christoph Hellwig <hch@infradead.org>
To: Greentime Hu <greentime.hu@sifive.com>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Subject: Re: [PATCH v10 05/16] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Sun, 15 May 2022 23:47:47 -0700	[thread overview]
Message-ID: <YoHzkxDmMegp5oOz@infradead.org> (raw)
In-Reply-To: <221f72a2ee62cd5350edb5d6a7e8ebb17a7bc321.1652257230.git.greentime.hu@sifive.com>

On Wed, May 11, 2022 at 08:31:15AM +0000, Greentime Hu wrote:
> +#ifdef CONFIG_VECTOR
> +#include <asm/vector.h>
> +EXPORT_SYMBOL(rvv_enable);
> +EXPORT_SYMBOL(rvv_disable);
> +#endif

As far as I can tell these are not used by any modular code, just by
the later added kernel mode vector enable helpers.

Even if they were used this would need to be EXPORT_SYMBOL_GPL.

> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2012 Regents of the University of California
> + * Copyright (C) 2017 SiFive
> + * Copyright (C) 2019 Alibaba Group Holding Limited
> + *
> + *   This program is free software; you can redistribute it and/or
> + *   modify it under the terms of the GNU General Public License
> + *   as published by the Free Software Foundation, version 2.
> + *
> + *   This program is distributed in the hope that it will be useful,
> + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *   GNU General Public License for more details.
> + */

No need for all the GPL boilerplate text when you have an SPDX tag.

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  reply	other threads:[~2022-05-16  6:47 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11  8:31 [PATCH v10 00/16] riscv: Add vector ISA support Greentime Hu
2022-05-11  8:31 ` [PATCH v10 01/16] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2022-05-11  8:31 ` [PATCH v10 02/16] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2022-05-11  8:31 ` [PATCH v10 03/16] riscv: Add new csr defines related to vector extension Greentime Hu
2022-05-11  8:31 ` [PATCH v10 04/16] riscv: Add vector feature to compile Greentime Hu
2022-05-11  8:31 ` [PATCH v10 05/16] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2022-05-16  6:47   ` Christoph Hellwig [this message]
2022-11-08 17:25     ` Vineet Gupta
2022-05-11  8:31 ` [PATCH v10 06/16] riscv: Reset vector register Greentime Hu
2022-05-11  8:31 ` [PATCH v10 07/16] riscv: Add vector struct and assembler definitions Greentime Hu
2022-05-11  8:31 ` [PATCH v10 08/16] riscv: Add task switch support for vector Greentime Hu
2022-05-11 14:54   ` kernel test robot
2022-05-11 17:28   ` kernel test robot
2022-05-11  8:31 ` [PATCH v10 09/16] riscv: Add ptrace vector support Greentime Hu
2022-05-11  8:31 ` [PATCH v10 10/16] riscv: Add sigcontext save/restore for vector Greentime Hu
2022-05-11  8:31 ` [PATCH v10 11/16] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2022-05-11  8:31 ` [PATCH v10 12/16] riscv: Add support for kernel mode vector Greentime Hu
2022-05-11  8:31 ` [PATCH v10 13/16] riscv: Add vector extension XOR implementation Greentime Hu
2022-05-11  8:31 ` [PATCH v10 14/16] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu
2022-05-14  8:56   ` Guo Ren
2022-05-11  8:31 ` [PATCH v10 15/16] riscv: Add V extension to KVM ISA allow list Greentime Hu
2022-05-11  8:31 ` [PATCH v10 16/16] riscv: KVM: Add vector lazy save/restore support Greentime Hu

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