Re: [PATCH AUTOSEL 5.19 08/48] riscv: dts: microchip: Add mpfs' topology information

Conor.Dooley
2022-08-14T16:31:34Z

On 14/08/2022 17:19, Sasha Levin wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> [ Upstream commit 88d319c6abaeb37f0e2323275eaf57a8388e0265 ]
>
> The mpfs has no cpu-map node, so tools like hwloc cannot correctly
> parse the topology. Add the node using the existing node labels.
>
+CC Greg

Hey Sasha,
Technically this is an optional property so I didn't mark any of
the patches as CC: stable as they not really fixes. The plan to is
to fix the hwloc problem at the source rather than papering over it
with the dts:
https://lore.kernel.org/linux-riscv/20220715175155.3567243-1-mail@conchuod.ie/

Those patches are delayed until after -rc1 as they weren't reviewed
from the riscv side prior to the arm64 tree closing, but the plan is
to backport those instead.

I suppose there's no harm having these too, but I'll leave that up
to the better judgement of others... What do you (plural) think?
Thanks,
Conor.

This applies to the following commits too:
riscv: dts: sifive: Add fu540 topology information
riscv: dts: sifive: Add fu740 topology information
riscv: dts: canaan: Add k210 topology information

> Reported-by: Brice Goglin <Brice.Goglin@inria.fr>
> Link: https://github.com/open-mpi/hwloc/issues/536
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index 496d3b7642bd..e3793916a1e5 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -142,6 +142,30 @@ cpu4_intc: interrupt-controller {
> interrupt-controller;
> };
> };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> + };
> + };
> };
>
> refclk: mssrefclk {