From: Conor Dooley <conor@kernel.org>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: linux-riscv@lists.infradead.org
Subject: Re: [PATCH] RISC-V: Re-enable counter access from userspace
Date: Wed, 28 Sep 2022 21:53:24 +0100 [thread overview]
Message-ID: <YzS0RNzH2CprLSyc@spud> (raw)
In-Reply-To: <20220928131807.30386-1-palmer@rivosinc.com>
On Wed, Sep 28, 2022 at 06:18:07AM -0700, Palmer Dabbelt wrote:
> These counters were part of the ISA when we froze the uABI, removing
> them breaks userspace.
>
> Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/
> Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Completely forgot about this and was wondering why my timer accessing,
userspace program was not working on an unmatched but did on an
icicle... This patch makes it work again :)
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> drivers/perf/riscv_pmu_sbi.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 6f6681bbfd36..e45daffbfb36 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -645,8 +645,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
> struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
> struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
>
> - /* Enable the access for TIME csr only from the user mode now */
> - csr_write(CSR_SCOUNTEREN, 0x2);
> + /*
> + * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,
> + * as is necessary to maintain uABI compatibility.
> + */
> + csr_write(CSR_SCOUNTEREN, 0x7);
>
> /* Stop all the counters so that they can be enabled from perf */
> pmu_sbi_stop_all(pmu);
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2022-09-28 20:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 13:18 [PATCH] RISC-V: Re-enable counter access from userspace Palmer Dabbelt
2022-09-28 13:39 ` Conor Dooley
2022-09-28 20:53 ` Conor Dooley [this message]
2022-10-13 19:45 ` Palmer Dabbelt
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