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Mon, 07 Apr 2025 11:21:23 -0700 (PDT) Received: from x1 ([97.115.235.21]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2297866e612sm84407055ad.200.2025.04.07.11.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 11:21:23 -0700 (PDT) Date: Mon, 7 Apr 2025 11:21:21 -0700 From: Drew Fustini To: Michal Wilczynski Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, guoren@kernel.org, wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v7 3/3] riscv: dts: thead: Add device tree VO clock controller Message-ID: References: <20250403094425.876981-1-m.wilczynski@samsung.com> <20250403094425.876981-4-m.wilczynski@samsung.com> <17d69810-9d1c-4dd9-bf8a-408196668d7b@samsung.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <17d69810-9d1c-4dd9-bf8a-408196668d7b@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250407_112124_495554_F5C40355 X-CRM114-Status: GOOD ( 30.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Apr 07, 2025 at 05:30:43PM +0200, Michal Wilczynski wrote: > > > On 4/5/25 01:16, Drew Fustini wrote: > > On Thu, Apr 03, 2025 at 11:44:25AM +0200, Michal Wilczynski wrote: > >> VO clocks reside in a different address space from the AP clocks on the > >> T-HEAD SoC. Add the device tree node of a clock-controller to handle > >> VO address space as well. > >> > >> Signed-off-by: Michal Wilczynski > >> --- > >> arch/riscv/boot/dts/thead/th1520.dtsi | 7 +++++++ > >> 1 file changed, 7 insertions(+) > >> > >> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > >> index 527336417765..d4cba0713cab 100644 > >> --- a/arch/riscv/boot/dts/thead/th1520.dtsi > >> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > >> @@ -489,6 +489,13 @@ clk: clock-controller@ffef010000 { > >> #clock-cells = <1>; > >> }; > >> > >> + clk_vo: clock-controller@ffef528050 { > >> + compatible = "thead,th1520-clk-vo"; > >> + reg = <0xff 0xef528050 0x0 0xfb0>; > > > > Thanks for your patch. It is great to have more of the clocks supported > > upstream. > > > > The TH1520 System User Manual shows 0xFF_EF52_8000 for VO_SUBSYS on page > > 205. Is there a reason you decided to use 0xFF_EF52_8050 as the base? > > > > I see on page 213 that the first register for VO_SUBSYS starts with > > VOSYS_CLK_GATE at offset 0x50. I figure you did this to have the > > CCU_GATE macros use offset of 0x0 instead 0x50. > > > > I kind of think the reg property using the actual base address > > (0xFF_EF52_8000) makes more sense as that's a closer match to the tables > > in the manual. But I don't have a strong preference if you think think > > using 0xef528050 makes the CCU_GATE macros easier to read. > > Thank you for your comment. > > This was discussed some time ago. The main issue was that the address > space was fragmented between clocks and resets. Initially, I proposed > using syscon as a way to abstract this, but the idea wasn't particularly > well received. > > So at the start of the 0xFF_EF52_8000 there is a reset register GPU_RST_CFG > I need for resetting the GPU. > > For reference, here's the earlier discussion: [1] > > [1] - https://lore.kernel.org/all/1b05b11b2a8287c0ff4b6bdd079988c7.sboyd@kernel.org/ Thanks for the explanation. Reviewed-by: Drew Fustini _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv