* [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
@ 2025-01-03 4:03 Stafford Horne
2025-01-10 2:29 ` Charlie Jenkins
2025-01-10 16:22 ` Mathieu Desnoyers
0 siblings, 2 replies; 6+ messages in thread
From: Stafford Horne @ 2025-01-03 4:03 UTC (permalink / raw)
To: LKML
Cc: Stafford Horne, Mathieu Desnoyers, Peter Zijlstra,
Paul E. McKenney, Boqun Feng, Shuah Khan, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-kselftest, linux-riscv
When working on OpenRISC support for restartable sequences I noticed
and fixed these two issues with the riscv support bits.
1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
passed to the macro. Fix this by adding 'inc' to the list of macro
arguments.
2 The inline asm input constraints for 'inc' and 'off' use "er", The
riscv gcc port does not have an "e" constraint, this looks to be
copied from the x86 port. Fix this by just using an "r" constraint.
I have compile tested this only for riscv. However, the same fixes I
use in the OpenRISC rseq selftests and everything passes with no issues.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
tools/testing/selftests/rseq/rseq-riscv.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
index de31a0143139..f02f411d550d 100644
--- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
+++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
@@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
#ifdef RSEQ_COMPARE_TWICE
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
#endif
- RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
+ RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
RSEQ_INJECT_ASM(4)
RSEQ_ASM_DEFINE_ABORT(4, abort)
: /* gcc asm goto does not allow outputs */
@@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
[ptr] "r" (ptr),
- [off] "er" (off),
- [inc] "er" (inc)
+ [off] "r" (off),
+ [inc] "r" (inc)
RSEQ_INJECT_INPUT
: "memory", RSEQ_ASM_TMP_REG_1
RSEQ_INJECT_CLOBBER
diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
index 37e598d0a365..67d544aaa9a3 100644
--- a/tools/testing/selftests/rseq/rseq-riscv.h
+++ b/tools/testing/selftests/rseq/rseq-riscv.h
@@ -158,7 +158,7 @@ do { \
"bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \
"333:\n"
-#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \
+#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
"mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \
RSEQ_ASM_OP_R_ADD(off) \
REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \
--
2.47.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
2025-01-03 4:03 [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm Stafford Horne
@ 2025-01-10 2:29 ` Charlie Jenkins
2025-01-10 9:56 ` Stafford Horne
2025-01-10 16:22 ` Mathieu Desnoyers
1 sibling, 1 reply; 6+ messages in thread
From: Charlie Jenkins @ 2025-01-10 2:29 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Mathieu Desnoyers, Peter Zijlstra, Paul E. McKenney,
Boqun Feng, Shuah Khan, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-kselftest, linux-riscv
On Fri, Jan 03, 2025 at 04:03:26AM +0000, Stafford Horne wrote:
> When working on OpenRISC support for restartable sequences I noticed
> and fixed these two issues with the riscv support bits.
>
> 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
> passed to the macro. Fix this by adding 'inc' to the list of macro
> arguments.
> 2 The inline asm input constraints for 'inc' and 'off' use "er", The
> riscv gcc port does not have an "e" constraint, this looks to be
> copied from the x86 port. Fix this by just using an "r" constraint.
>
> I have compile tested this only for riscv. However, the same fixes I
> use in the OpenRISC rseq selftests and everything passes with no issues.
Thank you for these changes! I suppose these tests hadn't been ran on
riscv before... I ran the tests on QEMU and they all passed :)
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
This should also have a fixes tag:
Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
> tools/testing/selftests/rseq/rseq-riscv.h | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> index de31a0143139..f02f411d550d 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> @@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> #ifdef RSEQ_COMPARE_TWICE
> RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
> #endif
> - RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
> + RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
> RSEQ_INJECT_ASM(4)
> RSEQ_ASM_DEFINE_ABORT(4, abort)
> : /* gcc asm goto does not allow outputs */
> @@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
> [rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
> [ptr] "r" (ptr),
> - [off] "er" (off),
> - [inc] "er" (inc)
> + [off] "r" (off),
> + [inc] "r" (inc)
> RSEQ_INJECT_INPUT
> : "memory", RSEQ_ASM_TMP_REG_1
> RSEQ_INJECT_CLOBBER
> diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
> index 37e598d0a365..67d544aaa9a3 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv.h
> @@ -158,7 +158,7 @@ do { \
> "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \
> "333:\n"
>
> -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \
> +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
> "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \
> RSEQ_ASM_OP_R_ADD(off) \
> REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \
> --
> 2.47.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
2025-01-10 2:29 ` Charlie Jenkins
@ 2025-01-10 9:56 ` Stafford Horne
0 siblings, 0 replies; 6+ messages in thread
From: Stafford Horne @ 2025-01-10 9:56 UTC (permalink / raw)
To: Charlie Jenkins
Cc: LKML, Mathieu Desnoyers, Peter Zijlstra, Paul E. McKenney,
Boqun Feng, Shuah Khan, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-kselftest, linux-riscv
On Thu, Jan 09, 2025 at 06:29:01PM -0800, Charlie Jenkins wrote:
> On Fri, Jan 03, 2025 at 04:03:26AM +0000, Stafford Horne wrote:
> > When working on OpenRISC support for restartable sequences I noticed
> > and fixed these two issues with the riscv support bits.
> >
> > 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
> > passed to the macro. Fix this by adding 'inc' to the list of macro
> > arguments.
> > 2 The inline asm input constraints for 'inc' and 'off' use "er", The
> > riscv gcc port does not have an "e" constraint, this looks to be
> > copied from the x86 port. Fix this by just using an "r" constraint.
> >
> > I have compile tested this only for riscv. However, the same fixes I
> > use in the OpenRISC rseq selftests and everything passes with no issues.
>
> Thank you for these changes! I suppose these tests hadn't been ran on
> riscv before... I ran the tests on QEMU and they all passed :)
Thanks for confirming.
> Tested-by: Charlie Jenkins <charlie@rivosinc.com>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
>
> This should also have a fixes tag:
>
> Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")
Right, If ok I think Palmer / the maintainer can add that when picking up the
patch. If requested I can add that to a v2 though.
-Stafford
> >
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
> > tools/testing/selftests/rseq/rseq-riscv.h | 2 +-
> > 2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> > index de31a0143139..f02f411d550d 100644
> > --- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
> > +++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> > @@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> > #ifdef RSEQ_COMPARE_TWICE
> > RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
> > #endif
> > - RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
> > + RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
> > RSEQ_INJECT_ASM(4)
> > RSEQ_ASM_DEFINE_ABORT(4, abort)
> > : /* gcc asm goto does not allow outputs */
> > @@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> > [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
> > [rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
> > [ptr] "r" (ptr),
> > - [off] "er" (off),
> > - [inc] "er" (inc)
> > + [off] "r" (off),
> > + [inc] "r" (inc)
> > RSEQ_INJECT_INPUT
> > : "memory", RSEQ_ASM_TMP_REG_1
> > RSEQ_INJECT_CLOBBER
> > diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
> > index 37e598d0a365..67d544aaa9a3 100644
> > --- a/tools/testing/selftests/rseq/rseq-riscv.h
> > +++ b/tools/testing/selftests/rseq/rseq-riscv.h
> > @@ -158,7 +158,7 @@ do { \
> > "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \
> > "333:\n"
> >
> > -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \
> > +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
> > "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \
> > RSEQ_ASM_OP_R_ADD(off) \
> > REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \
> > --
> > 2.47.0
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
2025-01-03 4:03 [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm Stafford Horne
2025-01-10 2:29 ` Charlie Jenkins
@ 2025-01-10 16:22 ` Mathieu Desnoyers
2025-01-13 22:59 ` Shuah Khan
1 sibling, 1 reply; 6+ messages in thread
From: Mathieu Desnoyers @ 2025-01-10 16:22 UTC (permalink / raw)
To: Stafford Horne, LKML
Cc: Peter Zijlstra, Paul E. McKenney, Boqun Feng, Shuah Khan,
Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-kselftest,
linux-riscv
On 2025-01-02 23:03, Stafford Horne wrote:
> When working on OpenRISC support for restartable sequences I noticed
> and fixed these two issues with the riscv support bits.
>
> 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
> passed to the macro. Fix this by adding 'inc' to the list of macro
> arguments.
> 2 The inline asm input constraints for 'inc' and 'off' use "er", The
> riscv gcc port does not have an "e" constraint, this looks to be
> copied from the x86 port. Fix this by just using an "r" constraint.
>
> I have compile tested this only for riscv. However, the same fixes I
> use in the OpenRISC rseq selftests and everything passes with no issues.
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> ---
> tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
> tools/testing/selftests/rseq/rseq-riscv.h | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> index de31a0143139..f02f411d550d 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> @@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> #ifdef RSEQ_COMPARE_TWICE
> RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
> #endif
> - RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
> + RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
> RSEQ_INJECT_ASM(4)
> RSEQ_ASM_DEFINE_ABORT(4, abort)
> : /* gcc asm goto does not allow outputs */
> @@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
> [rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
> [ptr] "r" (ptr),
> - [off] "er" (off),
> - [inc] "er" (inc)
> + [off] "r" (off),
> + [inc] "r" (inc)
> RSEQ_INJECT_INPUT
> : "memory", RSEQ_ASM_TMP_REG_1
> RSEQ_INJECT_CLOBBER
> diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
> index 37e598d0a365..67d544aaa9a3 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv.h
> @@ -158,7 +158,7 @@ do { \
> "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \
> "333:\n"
>
> -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \
> +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
> "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \
> RSEQ_ASM_OP_R_ADD(off) \
> REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \
--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
2025-01-10 16:22 ` Mathieu Desnoyers
@ 2025-01-13 22:59 ` Shuah Khan
2025-01-14 17:04 ` Stafford Horne
0 siblings, 1 reply; 6+ messages in thread
From: Shuah Khan @ 2025-01-13 22:59 UTC (permalink / raw)
To: Mathieu Desnoyers, Stafford Horne, LKML
Cc: Peter Zijlstra, Paul E. McKenney, Boqun Feng, Shuah Khan,
Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-kselftest,
linux-riscv, Shuah Khan
On 1/10/25 09:22, Mathieu Desnoyers wrote:
> On 2025-01-02 23:03, Stafford Horne wrote:
>> When working on OpenRISC support for restartable sequences I noticed
>> and fixed these two issues with the riscv support bits.
>>
>> 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
>> passed to the macro. Fix this by adding 'inc' to the list of macro
>> arguments.
>> 2 The inline asm input constraints for 'inc' and 'off' use "er", The
>> riscv gcc port does not have an "e" constraint, this looks to be
>> copied from the x86 port. Fix this by just using an "r" constraint.
>>
>> I have compile tested this only for riscv. However, the same fixes I
>> use in the OpenRISC rseq selftests and everything passes with no issues.
>>
>> Signed-off-by: Stafford Horne <shorne@gmail.com>
>
> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
>
If these are going through risc repo
Acked-by: Shuah Khan <skhan@linuxfoundation.org>
If you would like me to take this, let me know.
thanks,
-- Shuah
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
2025-01-13 22:59 ` Shuah Khan
@ 2025-01-14 17:04 ` Stafford Horne
0 siblings, 0 replies; 6+ messages in thread
From: Stafford Horne @ 2025-01-14 17:04 UTC (permalink / raw)
To: Shuah Khan
Cc: Mathieu Desnoyers, LKML, Peter Zijlstra, Paul E. McKenney,
Boqun Feng, Shuah Khan, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-kselftest, linux-riscv
On Mon, Jan 13, 2025 at 03:59:24PM -0700, Shuah Khan wrote:
> On 1/10/25 09:22, Mathieu Desnoyers wrote:
> > On 2025-01-02 23:03, Stafford Horne wrote:
> > > When working on OpenRISC support for restartable sequences I noticed
> > > and fixed these two issues with the riscv support bits.
> > >
> > > 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
> > > passed to the macro. Fix this by adding 'inc' to the list of macro
> > > arguments.
> > > 2 The inline asm input constraints for 'inc' and 'off' use "er", The
> > > riscv gcc port does not have an "e" constraint, this looks to be
> > > copied from the x86 port. Fix this by just using an "r" constraint.
> > >
> > > I have compile tested this only for riscv. However, the same fixes I
> > > use in the OpenRISC rseq selftests and everything passes with no issues.
> > >
> > > Signed-off-by: Stafford Horne <shorne@gmail.com>
> >
> > Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> >
>
> If these are going through risc repo
>
> Acked-by: Shuah Khan <skhan@linuxfoundation.org>
>
> If you would like me to take this, let me know.
Thanks, I have not heard from Palmer yet regarding what he wants to do. I will
send a v2 aggregating the Reviewed-by/Acked-by hopefully that will help.
-Stafford
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-01-14 17:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-03 4:03 [PATCH] rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm Stafford Horne
2025-01-10 2:29 ` Charlie Jenkins
2025-01-10 9:56 ` Stafford Horne
2025-01-10 16:22 ` Mathieu Desnoyers
2025-01-13 22:59 ` Shuah Khan
2025-01-14 17:04 ` Stafford Horne
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).