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Levin" , Andrea Bolognani , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Thomas Gleixner , Ron Economos , Andrew Jones , Quan Zhou , Felix Yan , Ruizhe Pan , Guo Ren , Yao Zi , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, stable@vger.kernel.org, =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Subject: Re: [PATCH v6 0/3] riscv/ptrace: add new regset to access original a0 register Message-ID: References: <20250115-riscv-new-regset-v6-0-59bfddd33525@coelacanthus.name> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250115-riscv-new-regset-v6-0-59bfddd33525@coelacanthus.name> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250115_144305_285875_DC9B36A7 X-CRM114-Status: GOOD ( 19.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Jan 15, 2025 at 07:13:26PM +0800, Celeste Liu wrote: > The orig_a0 is missing in struct user_regs_struct of riscv, and there is > no way to add it without breaking UAPI. (See Link tag below) > > Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to > access original a0 register from userspace via ptrace API. > > Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/ > > Signed-off-by: Celeste Liu > --- > Changes in v6: > - Fix obsolute comment. > - Copy include/linux/stddef.h to tools/include to use offsetofend in > selftests. > - Link to v5: https://lore.kernel.org/r/20250115-riscv-new-regset-v5-0-d0e6ec031a23@coelacanthus.name > > Changes in v5: > - Fix wrong usage in selftests. > - Link to v4: https://lore.kernel.org/r/20241226-riscv-new-regset-v4-0-4496a29d0436@coelacanthus.name > > Changes in v4: > - Fix a copy paste error in selftest. (Forget to commit...) > - Link to v3: https://lore.kernel.org/r/20241226-riscv-new-regset-v3-0-f5b96465826b@coelacanthus.name > > Changes in v3: > - Use return 0 directly for readability. > - Fix test for modify a0. > - Add Fixes: tag > - Remove useless Cc: stable. > - Selftest will check both a0 and orig_a0, but depends on the > correctness of PTRACE_GET_SYSCALL_INFO. > - Link to v2: https://lore.kernel.org/r/20241203-riscv-new-regset-v2-0-d37da8c0cba6@coelacanthus.name > > Changes in v2: > - Fix integer width. > - Add selftest. > - Link to v1: https://lore.kernel.org/r/20241201-riscv-new-regset-v1-1-c83c58abcc7b@coelacanthus.name > > --- > Celeste Liu (3): > riscv/ptrace: add new regset to access original a0 register > tools: copy include/linux/stddef.h to tools/include > riscv: selftests: Add a ptrace test to verify a0 and orig_a0 access > > arch/riscv/kernel/ptrace.c | 32 +++++ > include/uapi/linux/elf.h | 1 + > tools/include/linux/stddef.h | 85 ++++++++++++ > tools/include/uapi/linux/stddef.h | 6 +- > tools/testing/selftests/riscv/abi/.gitignore | 1 + > tools/testing/selftests/riscv/abi/Makefile | 6 +- > tools/testing/selftests/riscv/abi/ptrace.c | 193 +++++++++++++++++++++++++++ > 7 files changed, 319 insertions(+), 5 deletions(-) > --- > base-commit: 0e287d31b62bb53ad81d5e59778384a40f8b6f56 > change-id: 20241201-riscv-new-regset-d529b952ad0d > > Best regards, > -- > Celeste Liu > There is also this series that looks like it will solve this problem by providing an architecture agnostic way of changing syscall args with PTRACE_SET_SYSCALL_INFO [1]. - Charlie [1] https://lore.kernel.org/lkml/20250113170925.GA392@altlinux.org/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv