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Thu, 16 Jan 2025 13:09:21 -0800 (PST) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72dab9c8e37sm429311b3a.119.2025.01.16.13.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 13:09:20 -0800 (PST) Date: Thu, 16 Jan 2025 13:09:18 -0800 From: Charlie Jenkins To: Xu Lu Cc: anup@brainfault.org, tglx@linutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] irqchip: riscv: Order normal writes and IPI writes Message-ID: References: <20250116120710.51673-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250116120710.51673-1-luxu.kernel@bytedance.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250116_130922_066827_4B715C9C X-CRM114-Status: GOOD ( 15.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jan 16, 2025 at 08:07:10PM +0800, Xu Lu wrote: > Replace writel_relaxed() with writel() when issuing IPI to ensure all > previous write operations made by current CPU are visible to other CPUs. Did you experience an ordering issue from this? - Charlie > > Signed-off-by: Xu Lu > --- > drivers/irqchip/irq-riscv-imsic-early.c | 2 +- > drivers/irqchip/irq-thead-c900-aclint-sswi.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > index c5c2e6929a2f..275df5005705 100644 > --- a/drivers/irqchip/irq-riscv-imsic-early.c > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > @@ -27,7 +27,7 @@ static void imsic_ipi_send(unsigned int cpu) > { > struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); > > - writel_relaxed(IMSIC_IPI_ID, local->msi_va); > + writel(IMSIC_IPI_ID, local->msi_va); > } > > static void imsic_ipi_starting_cpu(void) > diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip/irq-thead-c900-aclint-sswi.c > index b0e366ade427..8ff6e7a1363b 100644 > --- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c > +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c > @@ -31,7 +31,7 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); > > static void thead_aclint_sswi_ipi_send(unsigned int cpu) > { > - writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu)); > + writel(0x1, per_cpu(sswi_cpu_regs, cpu)); > } > > static void thead_aclint_sswi_ipi_clear(void) > -- > 2.20.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv