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[99.152.116.91]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-a9bcc322a55sm11089789a12.27.2025.01.22.12.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 12:03:54 -0800 (PST) Date: Wed, 22 Jan 2025 12:03:48 -0800 From: Olof Johansson To: Yixun Lan Subject: Re: [PATCH v4 1/4] dt-bindings: gpio: spacemit: add support for K1 SoC Message-ID: References: <20250121-03-k1-gpio-v4-0-4641c95c0194@gentoo.org> <20250121-03-k1-gpio-v4-1-4641c95c0194@gentoo.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250121-03-k1-gpio-v4-1-4641c95c0194@gentoo.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250122_120356_315868_079B2265 X-CRM114-Status: GOOD ( 24.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Conor Dooley , Meng Zhang , linux-gpio@vger.kernel.org, Linus Walleij , linux-kernel@vger.kernel.org, Conor Dooley , Yangyu Chen , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Jesse Taube , Jisheng Zhang , Paul Walmsley , Inochi Amaoto , Krzysztof Kozlowski , Bartosz Golaszewski Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi, On Tue, Jan 21, 2025 at 11:38:11AM +0800, Yixun Lan wrote: > The GPIO controller of K1 support basic functions as input/output, > all pins can be used as interrupt which route to one IRQ line, > trigger type can be select between rising edge, failing edge, or both. > There are four GPIO ports, each consisting of 32 pins. > > Signed-off-by: Yixun Lan > --- > .../devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 116 +++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..dd9459061aecfcba84e6a3c5052fbcddf6c61150 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml > @@ -0,0 +1,116 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SpacemiT K1 GPIO controller > + > +maintainers: > + - Yixun Lan > + > +description: > + The controller's registers are organized as sets of eight 32-bit > + registers with each set of port controlling 32 pins. A single > + interrupt line is shared for all of the pins by the controller. > + Each port will be represented as child nodes with the generic > + GPIO-controller properties in this bindings file. There's only one interrupt line for all ports, but you have a binding that duplicates them for every set of ports. That seems overly complicated, doesn't it? They'd all bind the same handler, so there's no benefit in providing the flexibility,. > +properties: > + $nodename: > + pattern: "^gpio@[0-9a-f]+$" > + > + compatible: > + const: spacemit,k1-gpio > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > +patternProperties: > + "^gpio-port@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: spacemit,k1-gpio-port > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 > + > + gpio-ranges: true > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 2 > + description: > + The first cell is the GPIO number, the second should specify interrupt > + flag. The controller does not support level interrupts, so flags of > + IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW should not be used. > + Refer for valid flags. Same here, since there's no real flexibility between the banks, it might make sense to consider a 3-cell GPIO specifier instead, and having the first cell indicate bank. I could see this argument go in either direction, but I'm not sure I understand why to provide a gpio-controller per bank. Comparing to say Rockchip, where each bank has a separate interrupt line -- so there the granularity makes sense. -Olof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv