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Thu, 06 Feb 2025 09:54:27 -0800 (PST) Received: from tjeznach.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048adb10csm1636427b3a.66.2025.02.06.09.54.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 09:54:26 -0800 (PST) Date: Thu, 6 Feb 2025 09:54:24 -0800 From: Tomasz Jeznach To: Jason Gunthorpe Cc: Alim Akhtar , Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Lu Baolu , David Woodhouse , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Hector Martin , Palmer Dabbelt , Paul Walmsley , Robin Murphy , Samuel Holland , Suravee Suthikulpanit , Sven Peter , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Bagas Sanjaya , Joerg Roedel , Pasha Tatashin , patches@lists.linux.dev, David Rientjes , Matthew Wilcox Subject: Re: [PATCH 17/19] iommu/riscv: Update to use iommu_alloc_pages_node_lg2() Message-ID: References: <0-v1-416f64558c7c+2a5-iommu_pages_jgg@nvidia.com> <17-v1-416f64558c7c+2a5-iommu_pages_jgg@nvidia.com> <20250206131721.GF2960738@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250206131721.GF2960738@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250206_095428_301101_D872185E X-CRM114-Status: GOOD ( 16.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Feb 06, 2025 at 09:17:21AM -0400, Jason Gunthorpe wrote: > On Wed, Feb 05, 2025 at 09:30:05PM -0800, Tomasz Jeznach wrote: > > > @@ -161,9 +163,8 @@ static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu, > > > } else { > > > do { > > > const size_t queue_size = entry_size << (logsz + 1); > > > - const int order = get_order(queue_size); > > > > > > - queue->base = riscv_iommu_get_pages(iommu, order); > > > + queue->base = riscv_iommu_get_pages(iommu, queue_size); > > > queue->phys = __pa(queue->base); > > > > All allocations must be 4k aligned, including sub-page allocs. > > Oh weird, so it requires 4k alignment but the HW can refuse to support > a 4k queue length? > Spec allows that. Also, hardware accepts only physical page number (so far PAGE_SIZE == 4K for riscv) of the base address, ignoring page offset. > I changed it to this: > > + queue->base = riscv_iommu_get_pages( > + iommu, max(queue_size, SZ_4K)); > LGTM > > > } while (!queue->base && logsz-- > 0); > > > } > > > @@ -618,7 +619,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iomm > > > break; > > > } > > > > > > - ptr = riscv_iommu_get_pages(iommu, 0); > > > + ptr = riscv_iommu_get_pages(iommu, PAGE_SIZE); > > > if (!ptr) > > > return NULL; > > > > > > @@ -698,7 +699,7 @@ static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu) > > > } > > > > > > if (!iommu->ddt_root) { > > > - iommu->ddt_root = riscv_iommu_get_pages(iommu, 0); > > > + iommu->ddt_root = riscv_iommu_get_pages(iommu, PAGE_SIZE); > > > iommu->ddt_phys = __pa(iommu->ddt_root); > > > } > > Should these be SZ_4K as well or PAGE_SIZE? > SZ_4K. For now iommu/risc-v hardware always assumes PAGE_SIZE == 4K. > Thanks, > Jason Thanks, - Tomasz _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv