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Mon, 10 Feb 2025 09:10:32 -0800 (PST) Received: from ghost ([50.146.0.9]) by smtp.gmail.com with ESMTPSA id 00721157ae682-6f99fd557absm17268277b3.56.2025.02.10.09.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 09:10:31 -0800 (PST) Date: Mon, 10 Feb 2025 09:10:30 -0800 From: Charlie Jenkins To: Andrew Jones Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, jesse@rivosinc.com, Anup Patel Subject: Re: [PATCH 7/9] riscv: Prepare for unaligned access type table lookups Message-ID: References: <20250207161939.46139-11-ajones@ventanamicro.com> <20250207161939.46139-18-ajones@ventanamicro.com> <20250210-51cedc94f4cba8c96516adc5@orel> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250210-51cedc94f4cba8c96516adc5@orel> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250210_091034_188997_675B5734 X-CRM114-Status: GOOD ( 24.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Feb 10, 2025 at 10:43:18AM +0100, Andrew Jones wrote: > On Fri, Feb 07, 2025 at 05:22:52PM -0800, Charlie Jenkins wrote: > > On Fri, Feb 07, 2025 at 05:19:47PM +0100, Andrew Jones wrote: > > > Probing unaligned accesses on boot is time consuming. Provide a > > > function which will be used to look up the access type in a table > > > by id registers. Vendors which provide table entries can then skip > > > the probing. > > > > The access checker in my experience is only time consuming on slow > > hardware. Hardware that supports fast unaligned accesses isn't really > > impacted by this? > > That's true, but... > > > Avoiding a list of hardware that has slow/fast > > unaligned accesses in the kernel was the main reason for dynamically > > checking. > > ...I'm not sure why we should try to avoid determining hardware support > by its description when a description can be provided. I worry about scalability of this. This to me seems like a slippery slope of hardcoding performance tables into the kernel. There are a lot of riscv vendors and allowing anybody to add a table to the kernel to dynamically change behavior specifically for their hardware could become a maintainability nightmare. Avoiding this maintainability issue was the motivation for the runtime checker. > > > We did introduce the config option to compile the kernel with > > assumed slow/fast accesses, which of course has the downside of > > recompiling the kernel and I assume that you already considered that. > > yup > > > > > Instead of having a table in the kernel, something that would be more > > platform agnostic would be to have an extension that signals this > > information. That seems like it would accomplish the same goal and > > leverage the existing infrastructure in the kernel, albeit with the need > > to make a new extension. > > Yes, I agree that another profile "named feature" may be the best > approach. I'll consider proposing one, but [1] implies there may be Yeah that thread does highlight the unfortunate way that riscv has evolved, but I hope that wouldn't be a prohibiting factor here. - Charlie > some resistance to creating something like that. > > [1] https://github.com/riscv/riscv-isa-manual/issues/1611 > > Thanks, > drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv