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Thu, 20 Feb 2025 10:23:02 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7328acf354esm6281724b3a.3.2025.02.20.10.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 10:23:02 -0800 (PST) Date: Thu, 20 Feb 2025 10:23:00 -0800 From: Deepak Gupta To: Chunyan Zhang Cc: =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Chunyan Zhang , Palmer Dabbelt , Albert Ou , Paul Walmsley , Alexandre Ghiti , Andrew Morton , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Alistair Popple , linux-mm@kvack.org Subject: Re: [PATCH V5 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Message-ID: References: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> <20241113095833.1805746-2-zhangchunyan@iscas.ac.cn> <87frl0snf6.fsf@all.your.base.are.belong.to.us> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_102304_447567_CB7DB23D X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sorry for the late response. On Tue, Feb 11, 2025 at 04:05:02PM +0800, Chunyan Zhang wrote: >On Tue, 11 Feb 2025 at 12:01, Deepak Gupta wrote: >> >> On Tue, Feb 11, 2025 at 09:20:22AM +0800, Chunyan Zhang wrote: >> >On Thu, 30 Jan 2025 at 16:42, Bj=F6rn T=F6pel wrote: >> >> >> >> Chunyan Zhang writes: >> >> >> >> > The PTE bit(9) on RISC-V is reserved for software, it is used by de= vmap >> >> > now which has to be disabled if we want to use bit(9) for other fea= tures, >> >> > since there's no more free PTE bit on RISC-V now. >> >> > >> >> > So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as >> >> > the build condition of devmap definitions. >> >> >> >> Heads-up: It seems like Alistair's series [1] that removes the devmap >> >> PTE bit will most likely land in 6.15. >> > >> >Yes, I've been keeping an eye on Alistair's series, intended to update >> >this patchset after Alistair's patch that removes the devmap PTE bit >> >got merged. >> >> Please keep in mind that even after claiming back devmap PTE SW bit, a c= ompile >> time decision to select between uffd-wp and soft-dirty is not desirable. > >Yes, I agree. I've read your aother email. I also hope we can have >more RSW bits to use. So should we add uffd-wp and soft-dirty support >on RISC-V until we have two RSW bits for these two functions? Is an >undesirable solution better than no solution for now? Problem is that this undesirable solution doesn't solve anything for *most*= users. Kernel can't deviate from providing functionality (which is actually arch-a= gnostic) to user mode depending on the architecture. >I can optimize the code when we have more free RSW bits, that's not hard. We got 3 use cases, - pfnmap/pte_special - uffd-wp - softdirty 4th one for devmap, I hope we don't need to do it. Should get it back. https://lore.kernel.org/lkml/cover.95ff0627bc727f2bae44bea4c00ad7a83fbbcfac= .1739941374.git-series.apopple@nvidia.com/#r It looks like any work there would be wasted time. There is a (fast track) proposal out there to get 2 more RSW bits. https://lists.riscv.org/g/tech-privileged/message/2268 I hope it gets ratified soon. We will have proper solution to this problem = then. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv