Re: [PATCH v5 4/5] clk: spacemit: k1: Add TWSI8 bus and function clocks

From: Haylen Chu <heylenay@4d2.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Haylen Chu <heylenay@outlook.com>, Yixun Lan <dlan@gentoo.org>
Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	spacemit@lists.linux.dev, Inochi Amaoto <inochiama@outlook.com>,
	Chen Wang <unicornxdotw@foxmail.com>,
	Jisheng Zhang <jszhang@kernel.org>,
	Meng Zhang <zhangmeng.kevin@linux.spacemit.com>
Subject: Re: [PATCH v5 4/5] clk: spacemit: k1: Add TWSI8 bus and function clocks
Date: Fri, 7 Mar 2025 06:30:52 +0000	[thread overview]
Message-ID: <Z8qSnBc4dmR3ftOz@ketchup> (raw)
In-Reply-To: <20250306175750.22480-6-heylenay@4d2.org>

On Thu, Mar 06, 2025 at 05:57:50PM +0000, Haylen Chu wrote:
> The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux
> selection bits, reset assertion bit and enable bits for function and bus
> clocks. It has a quirk that reading always results in zero.
> 
> As a workaround, let's hardcode the mux value as zero to select
> pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask
> is combined from the real bus and function clocks to avoid the
> write-only register being shared between two clk_hws, in which case
> updates of one clk_hw zero the other's bits.
> 
> With a 1:1 factor serving as placeholder for the bus clock, the I2C-8
> controller could be brought up, which is essential for boards attaching
> power-management chips to it.
> 
> Signed-off-by: Haylen Chu <heylenay@4d2.org>
> ---
>  drivers/clk/spacemit/ccu-k1.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
> index 5974a0a1b5f6..44db48ae7131 100644
> --- a/drivers/clk/spacemit/ccu-k1.c
> +++ b/drivers/clk/spacemit/ccu-k1.c
> @@ -558,6 +558,10 @@ static CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents,
>  			   APBC_TWSI7_CLK_RST,
>  			   4, 3, BIT(1),
>  			   0);
> +static CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5),
> +		       APBC_TWSI8_CLK_RST,
> +		       BIT(1) | BIT(0),
> +		       0);
>  
>  static const struct clk_parent_data timer_parents[] = {
>  	CCU_PARENT_HW(pll1_d192_12p8),
> @@ -795,6 +799,8 @@ static CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk),
>  		       APBC_TWSI7_CLK_RST,
>  		       BIT(0),
>  		       0);
> +static CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk),
> +			 1, 1);
>  
>  static CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk),
>  		       APBC_TIMERS1_CLK_RST,
> -- 
> 2.48.1
> 

Oops, I don't split out the twsi8-related definitions completely from
PATCH 3, causing building errors with only PATCH 3 applied. Will fix it
in the next version.

Best regards,
Haylen Chu

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