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Wed, 12 Mar 2025 16:38:07 -0700 (PDT) Received: from localhost ([216.228.125.129]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c68883d0sm1323525ad.10.2025.03.12.16.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Mar 2025 16:38:06 -0700 (PDT) Date: Wed, 12 Mar 2025 19:38:04 -0400 From: Yury Norov To: Ignacio Encinas Cc: Rasmus Villemoes , Paul Walmsley , Palmer Dabbelt , linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: fix test_and_{set,clear}_bit ordering documentation Message-ID: References: <20250311-riscv-fix-test-and-set-bit-comment-v1-1-8d2598e1e43b@iencinas.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250311-riscv-fix-test-and-set-bit-comment-v1-1-8d2598e1e43b@iencinas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250312_163809_109088_E4A38B79 X-CRM114-Status: GOOD ( 21.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Mar 11, 2025 at 06:20:22PM +0100, Ignacio Encinas wrote: > test_and_{set,clear}_bit are fully ordered as specified in > Documentation/atomic_bitops.txt. Fix incorrect comment stating otherwise. > > Note that the implementation is correct since commit > 9347ce54cd69 ("RISC-V: __test_and_op_bit_ord should be strongly ordered") > was introduced. > > Signed-off-by: Ignacio Encinas Applied in bitmap-for-next. Thanks, Yury > --- > This seems to be a leftover comment from the initial implementation > which assumed these operations were relaxed. > > Documentation/atomic_bitops.txt states: > > [...] > RMW atomic operations with return value: > > test_and_{set,clear,change}_bit() > test_and_set_bit_lock() > [...] > > - RMW operations that have a return value are fully ordered. > > Similar comments can be found in > include/asm-generic/bitops/instrumented-atomic.h, > include/linux/atomic/atomic-long.h, etc... > --- > arch/riscv/include/asm/bitops.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > index c6bd3d8354a96b4e7bbef0e98a201da412301b57..49a0f48d93df5be4d38fe25b437378467e4ca433 100644 > --- a/arch/riscv/include/asm/bitops.h > +++ b/arch/riscv/include/asm/bitops.h > @@ -226,7 +226,7 @@ static __always_inline int variable_fls(unsigned int x) > * @nr: Bit to set > * @addr: Address to count from > * > - * This operation may be reordered on other architectures than x86. > + * This is an atomic fully-ordered operation (implied full memory barrier). > */ > static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long *addr) > { > @@ -238,7 +238,7 @@ static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long > * @nr: Bit to clear > * @addr: Address to count from > * > - * This operation can be reordered on other architectures other than x86. > + * This is an atomic fully-ordered operation (implied full memory barrier). > */ > static __always_inline int arch_test_and_clear_bit(int nr, volatile unsigned long *addr) > { > > --- > base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b > change-id: 20250311-riscv-fix-test-and-set-bit-comment-aa9081a27d61 > > Best regards, > -- > Ignacio Encinas _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv